This paper explores the application of reinforcement learning algorithms to the problem of calibrating and optimizing the performance of an integrated millimeter-wave (mmW) power amplifier (PA). The proposed calibration algorithm is aimed at compensating performance degradation while optimizing power efficiency, by finding the optimum values of a set of on-chip tuning knobs. The developed calibration solution is based on a multiagent deep reinforcement learning algorithm, in which a number of reinforcement learning agents learn to collaborate in order to optimize the complete set of specifications of the circuit under calibration. The proposed technique is validated based on post-layout simulation results of a tunable 60 GHz PA case study implemented in STMicroelectronics 55 nm CMOS technology.

An on-chip high-frequency sinusoidal signal generator with a calibration circuit based on a coarse-fine delay cell is presented in this work. The proposed signal generator is based on harmonic cancellation by adding scaled and time-shifted versions of a periodic signal. However, as we increase the target frequency of the generated signal, harmonic cancellation can be severely degraded by timing issues, degrading in turn the spectral purity of the generated signal. This paper proposes an architecture of a harmonic cancellation-based sinusoidal signal generator including a calibration circuit. The calibration circuit is based on a coarse-fine delay cell that can correct timing inaccuracies. Postlayout simulations of the proposed generator in FD-SOI 28 nm technology show a THD better than −60 dB in the frequency range from 173 MHz to 2 GHz.

There is today a lack of mature transistor-level compact models for the simulation of integrated circuits at cryogenic temperatures. This is particularly the case for the simulation of the noise behavior which is critical for most applications. In this paper, we aim at an efficient prediction of the white noise behavior of basic amplifying stages working at RF frequencies and cryogenic temperatures. For this, we propose the use of DC measurements that are incorporated in a Look-Up Table (LUT) and fed to a mathematical noise model. We illustrate the approach for the case of a transistor in common source configuration. The results of circuit simulation of the noise parameters in the standard temperature range are very close to the estimation of the same parameters using the LUT with just DC measurements. The approach can be readily extended to the analysis of circuits with multiple components. Next, the LUT approach is used for estimating the noise parameters at cryogenic conditions, considering DC measurements that have been carried out at these temperatures. The paper illustrates the feasibility of carrying out a cryogenic design using a LUT-based approach while accurate compact models are not yet available.

Harmonic cancellation techniques have been exploited for the on-chip generation of high-linearity sinusoidal test stimuli. The sinusoidal signal is generated by combining time-shifted and scaled versions of a periodical signal, in such a way that by properly choosing the time-shifts and weights, the lower order harmonics are canceled. However, process variations and mismatch can degrade the effectiveness of the harmonic cancellation, since precise time-shifts and scale ratios are required. In this regard, timing inaccuracies are especially harmful in the implementation of high-speed harmonic cancelling generators. In this paper, we propose an on-chip calibration architecture that can correct the phase-shift and duty-cycle of the signals with the help of a negative feedback loop. Electrical simulation results at transistor level show the feasibility of the calibration technique for a sinusoidal signal generator implemented in ST 28 nm FD-SOI technology. Obtained results show a Total Harmonic Distortion (THD) better than -60 dB after calibration in an output frequency range from 200 MHz to 4 GHz.

This paper presents an innovative integrated load-pull bench at 160 GHz. The proposed system, which is designed in a 55-nm BiCMOS technology, is tailored to deal with all of the measurement functions including signal generation, shaping, and magnitude and phase measurement. This system will allow precise characterization of Devices-Under-Test (DUTs) (i.e., circuits and/or devices) when integrated together with the DUT. In addition, the proposed system could also be envisioned as a System-on-Chip (SoC) that, when reported into an RF probe, could serve as a test bench for any integrated circuit.

This paper describes an on-chip instrument for the estimation of absolute and period random jitter of clock signals in the GHz range with a sub-picosecond resolution. A self-referenced technique is used to remove the need of a very clean external reference clock. The instrument has been designed in STMicroelectronics 28 nm FDSOI technology. By exploiting the fine delay control which can be achieved with this technology, simulation results haven shown a resolution down to 100 fs for GHz clock signals with a simple calibration procedure. The instrument meets the requirement of a small footprint while using a standard digital test interface to transfer data. It can be configured in different ways to suit the resolution and frequency of operation requirements.

Testing of analog circuits plays a very important role in achieving both reliability and low cost for IoT and automotive systems. It is a technological challenge including circuit design, signal processing algorithms and measurement methods. This session consists of three talks from industry and academia in this area.

On-chip sinusoidal signal generators are a key element for enabling a wide variety of DfT and BIST applications for AMS-RF integrated circuits. Harmonic cancellation techniques have been recently proposed for the efficient implementation of high-quality embedded sinusoidal signal generators. However, harmonic cancellation techniques, based on phase-shifting and combining a set of periodic signals, rely on precise and accurate phase-shift control which makes them very sensitive to timing issues due to mismatch, noise, etc. Timing issues can severely limit the performance of these generators especially in high-frequency applications where precise timing becomes challenging. In this paper, we analyze the effects of timing inaccuracies on high-speed harmonic cancellation generators and we propose circuit techniques for mitigating them. Electrical simulation results on a 1.45 GHz sinusoidal signal generator implemented in ST 28 nm FDSOI technology are provided to validate our proposals.

This paper describes a BIST technique for the static linearity test of$V_{cm}$-based successive-approximation analog-to-digital converters (SAR ADCs). We discuss the application of reduced-code techniques for the$V_{cm}$-based SAR ADC topology and present a practical on-chip implementation based on an embedded incremental ADC. Simulation results are provided for validating the feasibility and performance of the proposed on-chip reduced-code static linearity test.

The disruptive potential of the IEEE 1687 standard does not come from a single innovation, but rather from its capacity of providing a unified framework where heterogeneous approaches can co-exist and interact. In this Special Session, we will present the complementary research activities performed in the TIMA laboratory covering different aspects of the standard (Mixed-Signal instrument testing, Embedded Aging Monitors and Test Access Securization), and their coordination thanks to the Manager-for SoC Test (MAST) software environment.

Analog/RF built-in test (BIT) techniques are essential for reducing the very high costs of specification-based tests and for high-safety applications. The adoption of a BIT technique needs to be decided at the design stage, and this can be facilitated by estimating the test quality in terms of errors such as test escapes (TE) and yield loss (YL). Test quality estimation at the design stage has been traditionally very difficult for analog/RF circuits due to the lack of fault models that properly cover parametric faulty behavior. In recent years, statistical simulation has been considered in combination with learning techniques for the estimation of parametric test metrics. Extreme value theory (EVT) has provided a rigorous tool for the computation of parametric test metrics. However, test metrics estimation has been limited to the use of a univariate model. In this paper, we extend this approach by using a multivariate extreme value model. We illustrate this for the evaluation of an RF LNA BIT technique using a bivariate model.

The test of analog, mixed-signal and RF (AMS-RF) circuits is still considered as a matter of human creativity, and although many attempts have been made towards their automation, no accepted and complete solution is yet available. Indeed, capturing the design knowledge of an experienced analog designer is one of the key challenges faced by the Electronic Design Automation (EDA) community. In this paper we explore the use of causal inference tools in the context of AMS-RF design and test with the goal of defining a methodology for uncovering the root causes of performance variation in these systems. We believe that such an analysis can be a promising first step for future EDA algorithms for AMS-RF systems.

This work presents the design, integration and experimental validation of an on-chip sinusoidal signal generator for analog and mixed signal Built-In Self-Test applications. The integrated generator is based on a calibrated harmonic cancellation strategy, previously presented by the authors, that consists in combining five digital square-waves with appropriate phase-shifts and scale weights. The generator employs a digital shift-register to provide a set of phase-shifted digital square-wave signals. These square-wave signals are then scaled and combined using controlled current sources. The proof-of-concept prototype of the sinusoidal signal generator was integrated in STMicroelectronics 28 nm FDSOI technology and characterized in the laboratory to validate the feasibility of the proposal. Obtained results show a performance of 52 dB of SFDR for a generated sinusoidal signal at 166.67 MHz. The generator was tested in an operation frequency range from 1 MHz to 333 MHz.

Integrated millimeter-wave (mm-wave) circuits fabricated in current nanometric processes are especially sensitive to process variations. This issue produces shifts in the circuit performance that may significantly reduce the fabrication yield. In this line, per-die characterization and trimming are usually required for mm-wave integrated circuits, but this is an expensive and time-consuming task to be performed at the production line. Embedded calibration for mm-wave circuits is an appealing alternative to enhance yield that may overcome some of these issues. In this work we present a two-stage 60 GHz power amplifier (PA), designed in STMicroelectronics 55 nm CMOS technology, that features a one-shot calibration procedure for process variation compensation based on non-intrusive process monitors. We present the design of a tuning knob based on variable decoupling cells which have been implemented within the PA for calibration purposes. The proposed one-shot calibration procedure reads the output of the embedded process monitors and then relies on a machine learning regression model to find the best configuration of the tuning knobs for optimizing the performance of the circuit and enhance fabrication yield.

This work presents reduced-code strategies for the static linearity test of successive-approximation analog-to-digital converters. Reduced-code techniques for ADC static linearity test may drastically reduce the test time for static linearity characterization. These techniques take advantage of the repetitive operation of SAR ADCs for reducing the number of necessary measurements for static linearity testing. In this paper we discuss the implementation of these techniques for three widely used SAR ADC topologies. Namely, we consider SAR ADCs based on binary-weighted capacitive DACs, split-capacitor DACs and segmented DACs. The proposed techniques are validated by behavioral simulations on three SAR ADC case studies.

This paper presents an on-chip stepwise ramp stimulus generator aimed at static linearity test applications for analog-to-digital converters (ADCs). The proposed ramp stimulus generator is based on a simple switched-capacitor integrator with a constant dc input. The integrator has been conveniently modified to produce a very small integration gain proportional to the capacitance difference of two capacitors, in such a way that the resulting stepwise ramp signal at the output has a step size below the least significant bit (LSB) of the target ADC under test. In order to verify the feasibility of the proposed ramp generation technique, this paper details the design and experimental characterization of a proof-of-concept stepwise ramp generator in a 65-nm CMOS technology. Experimental results on 15 fabricated samples show an average linearity of 14.5 effective bits in a differential output range of ±2 V. Moreover, a discrete-time static linearity measurement strategy is proposed and, as a proof-of-concept validation, it is verified on an off-the-shelf 11-bit ADC using the fabricated generator samples. Experimental results show an accuracy of ±0.3 LSB in the measurement of the integral nonlinearity of the ADC under test.

The functional test of millimeter-wave (mm-wave) circuitry in the production line is a challenging task that requires costly dedicated test equipment and long test times. Machine learning indirect test offers an appealing alternative to standard mm-wave functional test by replacing the direct measurement of the circuit performances by a set of indirect measurements, usually called signatures. Machine learning regression algorithms are then used to map signatures and performances. In this work, we present a generic and automated methodology for finding an appropriate set of indirect measurements and assisting the designer with the necessary Design-for-Test circuit modifications. In order to avoid complex design modifications of mm-wave circuitry, the proposed strategy is targeted at generating a set of non-intrusive indirect measurements using process variation sensors not connected to the Device Under Test (DUT). The proposed methodology is demonstrated on a 60 GHz Power Amplifier designed in STMicroelectronics 55 nm BiCMOS technology.

This work presents a strategy for static linearity self-testing of successive-approximation analog to digital converters (SAR ADCs) with the goal of reducing test time. The proposed test technique takes advantage of the SAR ADC architecture to drastically reduce the number of necessary measurements for a complete static linearity characterization. Moreover, we show that static linearity measurements can be performed on-chip without the need of a test stimulus generator, by generating the major carrier transitions of the SAR ADC and acquiring them with a low resolution ADC. The proposed test circuitry is reduced to a simple incremental ΣΔ ADC. The technique is validated with behavioral simulations and the design trade-offs of the proposed test circuitry are explored.

This work presents the design of a high-frequency on-chip sinusoidal signal generator based on a calibrated harmonic cancellation strategy. The proposed generator employs a digital shift-register to provide a set of phase-shifted digital square-wave signals. These square-wave signals are scaled and combined using a harmonic cancellation strategy in a simplified current-steering DAC with only five branches. The proposed architecture allows the cancellation of all harmonic components up to the eleventh. Additionally, a simple calibration strategy has been devised to compensate the impact of process variations and mismatch on the effectiveness of the harmonic cancellation. The simplicity of the circuitry makes this approach suitable for mixed-signal BIST applications. Electrical simulations of a 28 nm FDSOI design are provided to validate the functionality of the proposed signal generator. Obtained results show a calibrated performance around 70 dB of SFDR for a generated sinusoidal signal at 166 MHz.

Current mixed-signal BIST approaches are aimed to move test instrumentation on-chip to reduce the cost of test. However, this can result in a high overhead even for non-time critical DSP tasks that could be executed remotely if a suitable access was available. The new IEEE 1687-2014 standard provides such a portable and efficient infrastructure and can allow decoupling of digital and analog development extremely early in the design flow. In this paper, we demonstrate the approach by applying it to a ΣΔ modulator BIST. In this case study, we exploit 1687 to offload the computationally-heavy spectral analysis that may be responsible of nearly 80% of the total BIST overhead.

This work presents an efficient modification of the classical servo-loop static test setup aimed at the on-chip implementation of reduced-code static linearity test techniques. The proposed modified servo-loop provides a direct measurement of the width of a given ADC code without the need of an integrated voltmeter. The proposed measurement strategy is based on using a controlled step-wise ramp stimulus generator for exciting the ADC under test in such a way that the measurement of a code width can be determined in the digital domain by simply counting the number of ramp steps between two consecutive ADC output transitions. Moreover, the ability of the proposed servo-loop to target a given ADC code makes it very suitable for implementing advanced reduced-code static test techniques. This work analyses the performance limits of the proposed discrete-time servo-loop technique and explores its application to reduced-code linearity testing of pipeline ADCs.

This paper presents a self-testable BIST application for non-linearity test in high-speed high-performance ADCs in nanometric CMOS technologies. The technique makes use of an on-chip low-frequency signal generator optimized toward high accuracy, followed by a dedicated buffer based on a resistive feedback amplifier. This buffer has two main features: it isolates the on-chip generator output from the high-frequency switching noise at the input sampling of the ADC under test, and it allows a robust injection of a controlled offset to apply double-histogram techniques for linearity evaluation. This approach results in a true self-testable BIST strategy making feasible the simultaneous estimation of the non-linearity for both the generator and the ADCUT. In order to verify the feasibility and performance of the proposed circuitry, a practical design in a 1.8V 0.18μm CMOS process is presented here as demonstrator. Transistor-level simulation results with a 2Vpp sinusoidal test-stimulus show an effective resolution in static conditions greater than 15 bits, being a suitable solution for the ADC static test with effective resolutions in the order of 13 bits and 100Msps of sampling frequency.

This paper presents an Embedded Test Instrument (ETI) for the estimation of the High Frequency (HF) jitter of an observed clock signal. The ETI uses a second reference clock for under-sampling the observed signal similar to previous approaches. However, the analysis of the test response does not require the construction of the Cumulative Distributed Function (CDF) of the jitter as in previous approaches. Instead, the HF jitter of the input observed signal is transformed at the output of the ETI into a digital value that corresponds to a number of unwanted signal transitions. We demonstrate in this paper that the transfer function of the ETI defined by the ratio of the number of unwanted signal transitions and the input HF jitter is linear. This property leads to a simple circuit implementation. The linearity of the ETI is demonstrated firstly by behavioral simulation, using a theoretical model of the output of the under-sampling process, and secondly by transistor-level simulation using the 65 nm CMOS bulk technology by ST Microelectronics. We also present experimental measurements that have been carried out using an FPGA-based test platform to validate the linearity of the transfer function in the presence of non-idealities that can affect the ETI. Finally, we demonstrate the exploitation of the ETI within Systems-on-Chip (SoCs) produced in highvolume by ST Microelectronics.

The high cost of mixed-signal circuit testing has sparked a lot of interest for developing alternative low-cost techniques. Although it is rather straightforward to evaluate an alternative test technique in terms of test cost reduction, proving the equivalence between an alternative and the standard test technique in terms of test metrics, before actually deploying the alternative test technique in production, is very challenging. The underlying reason is the prohibitive simulation effort that is required. Existing test metrics evaluation methodologies are efficient only for circuits that can be simulated fast at transistor-level. In this paper, we propose a test metrics evaluation methodology for circuits with long simulation times that is based on a combination of behavioral modeling and statistical blockade. The methodology is demonstrated on a built-in self-test strategy for ΣΔ analog-to-digital converters.

Current production testing of CMOS imager sensors is mainly based on capturing images and detecting failures by image processing with special algorithms. The fault coverage of this costly optical test is not sufficient given the quality requirements. Studies on devices produced at large volume have shown that Horizontal Fixed Pattern Noise (HFPN) is one of the common image failures encountered on products that present fault coverage problems, and this is the main cause of customer returns for many products. A detailed analysis of failed devices has demonstrated that HFPN failures arise from changes of electronic circuit topology in pixel addressing decoders or the metal lines required for pixel powering and control. These changes are usually due to the presence of spot defects, causing some pixels in a row to operate incorrectly, leading to an HFPN failure. Moreover, defects resulting in partially degraded metal lines may not induce image failure in limited industrial test conditions, passing the optical tests. Later, these defects may produce an image failure in the field, either because the capture conditions would be more stringent, or because the defects would evolve into catastrophic faults due to electromigration. In this paper, we have first enhanced the HFPN detection algorithm in order to improve the fault coverage of the optical test. Next, a built-in self-test structure is presented for the on-chip detection of catastrophic and non-catastrophic defects in the pixel power and control lines.

Testing analog integrated circuits is expensive in terms of both test equipment and time. To reduce the cost, Design-For-Test techniques (DFT) such as Built-In Self-Test (BIST) have been developed. For a given Circuit Under Test (CUT), the choice of a suitable technique should be made at the design stage as a result of the analysis of test metrics such as test escapes and yield loss. However, it is very hard to carry out this estimation for analog/RF circuits by using fault simulation techniques. Instead, the estimation of parametric test metrics is made possible by Monte Carlo circuit-level simulations and the construction of statistical models. These models represent the output parameter space of the CUT in which the test metrics are defined. In addition, models of the input parameter space may be required to accelerate the simulations and obtain higher confidence in the DFT choices. In this work, we describe a methodological flow for the selection of most adequate statistical models and several techniques that can be used for obtaining these models. Some of these techniques have been integrated into a Computer-Aided Test (CAT) tool for the automation of the process of test metrics estimation. This estimation is illustrated for the case of a BIST solution for CMOS imager pixels that requires the use of advanced statistical modeling techniques.

Linearity testing for ADCs is one of the most resource and time consuming tasks in the production test of a mixed-signal integrated system. Advanced strategies for reducing static test time, such as the reduced code linearity test technique, have been recently presented. However, the application of these techniques require a high linearity input stimulus to excite the ADC under test, which is usually provided by an external analog signal generator in the ATE. Extending the static linearity test to a BIST implementation requires to include this generator on-chip, which is a challenging task. This paper explores different possibilities for the on-chip implementation of such generators.

In the context of mission-critical, safety-critical, and remote-controlled applications, it is required to equip systems with self-adapting capabilities. Adaptation is required in post-manufacturing to correct yield loss and achieve zero defective parts-per-million as well as during normal operation to account for different application scenarios and for varying environmental conditions. A self-adaptive system must be capable of providing the required high performances after manufacturing and throughout its normal operation regardless the application scenario wherein it is deployed and despite the varying environmental conditions. In this paper, we describe a generic post-manufacturing self-adaptation technique for RF circuits as well as concurrent self-adaptation techniques for a safety-critical medical sensor for glaucoma diagnosis and for a NFC system which is very sensitive to the environment in which it operates.

Validation of an embedded test technique in terms of its expected yield loss and test escape metrics is a key step before it can be deployed in high-volume manufacturing. However, performing this validation at the design stage usually demands extensive computational resources, which may render electrical simulations infeasible. In this paper, we propose a digital test technique for dynamic test of ΣΔ ADCs based on a digital ternary stimulus together with an advanced simulation framework for its validation. The proposed simulation strategy relies on a combination of transistor-level simulations, behavioural simulations, and statistical tools. To show the feasibility of our approach, we use the proposed validation framework to compare the ternary stimulus with a digital bitstream stimulus, as well as with a standard high-resolution analog sine-wave stimulus.

This paper proposes a new technique for the optimization of multi-frequency tests for linear analog circuits. Fault simulation is used to obtain the frequency intervals for the detection of each fault. New efficient algorithms are then presented for the selection of the optimal set of test frequencies within these intervals for the detection of all faults. Numerical simulations with randomly generated problem instances demonstrate the good time complexity of the proposed algorithms, with a large improvement over previous approaches (Mir et al 1996).

In this summary paper, we discuss two types of sensors that provide a built-in test solution for RF circuits. The key characteristic of the sensors is that they are non-intrusive, in the sense that they are not electrically connected to the RF circuit under test. This has the important advantage that the design of the RF circuit becomes totally independent from the design of the sensors. In other words, the RF circuit design methodology and performance trade-offs are totally transparent to the insertion of the built-in test strategy. In particular, we propose variation-aware sensors to implement an implicit functional test and a temperature sensor to implement a defect-oriented test. The proposed sensors provide DC or low-frequency measurements, thus they have the potential to reduce drastically the test cost. We discuss the principle of operation of the sensors, we provide design guidelines, and we demonstrate the concept on a set of fabricated chips. To the best of our knowledge, this is the first proof-of-concept of RF test based on non-intrusive sensors.

Fault diagnosis of Integrated Circuits (ICs) has grown into a special field of interest in the Semiconductor Industry. Fault diagnosis is very useful at the design stage for debugging purposes, at high-volume manufacturing for obtaining feedback about the underlying fault mechanisms and improving the design and layout in future IC generations, and in cases where the IC is part of a larger safety-critical system (e.g. automotive, aerospace) for identifying the root-cause of failure and for applying corrective actions that will prevent failure reoccurrence and, thereby, will expand the safety features. In this summary paper, we present a methodology for fault modeling and fault diagnosis of analog circuits based on machine learning. A defect filter is used to recognize the type of fault (parametric or catastrophic), inverse regression functions are used to locate and predict the values of parametric faults, and multi-class classifiers are used to list catastrophic faults according to their likelihood of occurrence. The methodology is demonstrated on both simulation and high-volume manufacturing data showing excellent overall diagnosis rate.

In this paper we show that the problem of minimizing the number of test frequencies necessary to detect all possible faults in a multi-frequency test approach for linear analog circuits can be modeled as a set covering problem. We will show in particular, that under some conditions on the considered faults, the coefficient matrix of the problem has the strong consecutive-ones property and hence the corresponding set covering problem can be solved in polynomial time. For an efficient solution of the problem, an interval graph formulation is also used and a polynomial algorithm using the interval graph structure is suggested. The optimization of test frequencies for a case-study biquadratic filter is presented for illustration purposes. Numerical simulations with a set of randomly generated problem instances demonstrate two different implementation approaches to solve the optimization problem very fast, with a good time complexity.

We present a built-in, defect-oriented test approach for RF circuits that is based on thermal monitoring. A defect will change the power dissipation of the circuit under test from its expected range of values which, in turn, will induce a change in the expected temperature in the substrate near the circuit. Thus, an on-chip temperature sensor that monitors the temperature near the circuit can reveal the existence of the defect. This test approach has the key advantage of being non-intrusive and transparent to the design since the temperature sensor is not electrically connected to the circuit. We discuss the basics of thermal monitoring, the design of the temperature sensor, as well as the test scheme. The technique is demonstrated on fabricated chips where a temperature sensor is employed to monitor an RF low noise amplifier.

Reduced code testing of a pipeline analog-to-digital converter (ADC) consists of inferring the complete static transfer function by measuring the width of a small subset of codes. This technique exploits the redundancy that is present in the way the ADC processes the analog input signal. The main challenge is to select the initial subset of codes such that the widths of the rest of the codes can be estimated correctly. By applying the state-of-the-art technique to a real 11-bit 2.5-bit/stage, 55nm pipeline ADC, we observed that the presence of noise affected the accuracy of the estimation of the static performances (e.g, differential nonlinearity and integral non-linearity). In this paper, we exploit another feature of the redundancy to cancel out the effect of noise. Experimental measurements demonstrate that this reduced code testing technique estimates the static performances with an accuracy equivalent to the standard histogram technique. Only 6 % of the codes need to be considered which represents a very significant test time reduction.

We present a set of sensors that enable a built-in test in RF circuits. The key characteristic of these sensors is that they are non-intrusive, that is, they are not electrically connected to the RF circuit, and, thereby, they do not degrade its performances. In particular, the presence of spot defects is detected by a temperature sensor, whereas the performances of the RF circuit in the presence of process variations are implicitly predicted by process sensors, namely dummy circuits and process control monitors. We discuss the principle of operation of these sensors, their design, as well as the test strategy that we have implemented. The idea is demonstrated on an RF low noise amplifier using post-layout simulations.

The reduced code linearity test technique for pipeline ADCs consists in measuring some judiciously selected codes which contain the information about the linearity of the converter as opposed to the standard histogram technique that considers indiscriminately all codes. This technique dramatically reduces the static test time for pipeline ADCs. In this paper, we identify some limitations in the existing version of the technique and we provide solutions to enhance its accuracy. The enhanced technique is applied to a 12-bit 2.5-bit/stage pipeline ADC.

This paper discusses a new type of sensors to enable a built-in test in RF circuits. The proposed sensors provide DC or low-frequency measurements, thus they can reduce drastically the testing cost. Their key characteristic is that they are nonintrusive, e.g. they are not connected electrically to the RF circuit. Thus, the performances of the RF circuit are unaffected by the monitoring operation. The sensors function as process monitors and share the same environment with the RF circuit. The underlying principle is that the sensors and the RF circuit are subject to the same process variations, thus shifts in the performances of the RF circuit can be inferred implicitly by shifts in the outputs of the sensors. We present experimental results on fabricated samples that include an LNA with embedded sensors. The samples are collected from different sites of a wafer such that they exhibit process variations. We demonstrate that the performances of the RF circuit can be predicted with sufficient accuracy through the sensors by employing the alternate test paradigm.

Ordering of analog/RF tests is important for the identification of redundant tests. Most methods for test ordering are based on a representative set of defective devices. However, at the beginning of production testing, there is little or no data on defective devices. Obtaining this data through defect and fault simulation is unrealistic for most advanced analog/RF devices. In this work, we will present a method for analog/RF test ordering that uses only data from a small set of functional circuits. A statistical model of the device under test is constructed from this data. This model is next used for sampling a large number of virtual circuits which will also include defective ones. These virtual defective circuits are then used for ordering analog/RF tests using feature selection techniques. Experimental results for an IBM RF front-end have demonstrated the validity of this technique for test grading and compaction.

In this paper we present the theory for evaluating the test error that we commit when we replace a standard analog test by a lower-cost alternative measurement. The evaluation takes place during the design and test development phases and relies on a tractable number of simulations. The test error is expressed in terms of test escape and yield loss which are estimated in parts per million accuracy. The theory is demonstrated with an example. In particular, we evaluate whether a dedicated on-chip envelope detector can be used to eliminate the NF test for an LNA.

A new technique for the estimation of analog parametric test metrics at the design stage is presented in this paper. This technique employs the copulas theory to estimate the distribution between random variables that represent the performances and the test measurements of the circuit under test (CUT). A copulas-based model separates the dependencies between these random variables from their marginal distributions, providing a complete and scale-free description of dependence that is more suitable to be modeled using well-known multivariate parametric laws. The model can be readily used for the generation of an arbitrarily large sample of CUT instances. This sample is thereafter used for estimating parametric test metrics such as defect level (or test escapes) and yield loss. We demonstrate the usefulness of the proposed technique to evaluate a built-in-test technique for a radio frequency low noise amplifier and to set test limits that result in a desired tradeoff between test metrics. In addition, we compare the proposed technique with previous ones that rely on direct density estimation.

This paper discusses a Bayesian fault diagnosis scheme for RF circuits. We use non-idealized spot defect models by taking into account both their resistive and capacitive behavior at the layout level. The likelihoods in the Bayes rule are estimated using nonparametric kernel density estimation. Our case study is an RF low noise amplifier. The diagnosis decisions and the subsequent defect ambiguity analysis are demonstrated using post-layout simulations.

We discuss a fault diagnosis scheme for analog integrated circuits. Our approach is based on an assemblage of learning machines that are trained beforehand to guide us through diagnosis decisions. The central learning machine is a defect filter that distinguishes failing devices due to gross defects (hard faults) from failing devices due to excessive parametric deviations (soft faults). Thus, the defect filter is key in developing a unified hard/soft fault diagnosis approach. Two types of diagnosis can be carried out according to the decision of the defect filter: hard faults are diagnosed using a multi-class classifier, whereas soft faults are diagnosed using inverse regression functions. We show how this approach can be used to single out diagnostic scenarios in an RF low noise amplifier (LNA).

The paper discusses a variety of sensors to enable a built-in test in RF devices. The list of sensors includes dummy circuits, process control monitors, DC probes, an envelope detector, and a current sensor. Dummy circuits and process control monitors are simple circuits that do not tap into the signal path of the RF device. Instead, they monitor the device by virtue of being subject to the same process variations. Their outputs form an alternative measurement pattern which can be mapped to the performances of the device using a typical alternate test flow. The rest of the sensors are physically connected to the RF device, thus they can detect random catastrophic defects within it and, as an auxiliary benefit, they can improve the accuracy in predicting its performances. The degradation that these sensors incur is carefully assessed and the RF device is co-designed with them to correct for the losses. The operation and test efficiency of the sensors is demonstrated for the case of an RF LNA using post-layout simulations.

Alternate RF testing is a very promising candidate for replacing the costly standard specification-based approach. The defect filter in the alternate test flow is a crucial preparatory step for the overall success of alternate test. In this paper, we present a novel nonlinear defect filter based on an estimate of the joint probability density function of the alternate measurements. The construction of the filter does not require a defect dictionary and can accommodate any underlying density without needing any prior knowledge regarding its parametric form.

The high cost of analog circuit testing has sparked off intensified efforts to identify robust and low-cost alternative tests that could effectively replace the standard specification-based tests. Nevertheless, the current practice is still specification-based testing. One of the primary reasons is the lack of tools to evaluate in advance the indirect costs (e.g. parametric test escape and yield loss) associated with alternative tests. To this end, in this paper, we present a method to estimate test escape and yield loss that occur as a result of replacing one costly specification test by one low-cost alternative test. This evaluation is performed at the design or test development stage with parts per million (PPM) accuracy. The method is based on extreme value theory and on a fast simulation technique of extreme events called statistical blockade.

This paper presents a new approach for controlling power consumption in RF devices. The approach is based on the definition of application-dependent performance modes for power hungry RF circuits and a logical control strategy that adjusts the power supply of each circuit to the mode required by the application. The control strategy uses embedded sensors, a recursive parameter identification approach and regression models for performance prediction, while demanding minimum embedded resources for computation. The control strategy is robust with respect to circuit parametric deviations due to the manufacturing process or ageing mechanisms. The strategy is illustrated for the case of an RF LNA using envelope detectors as embedded sensors. Simulation results of the control strategy at the transistor-level illustrate the energy savings that can be obtained for an example application.

This paper presents an approach for ordering analog specification (or functional) tests that is based on a statistical estimation of parametric defect level. A statistical model of n specification tests is obtained by applying a density estimation technique to a small sample of data (obtained from the initial phase of production testing or through Monte-Carlo simulation of the design). The statistical model is next sampled to generate a large population of synthetic devices from which specification tests can be ordered according to their impact on defect level by means of feature selection techniques. An optimal order can be obtained using the Branch and Bound method when n is relatively low. However, for larger values of n, heuristic methods such as genetic algorithms and floating search must be used which do not guarantee an optimal order. Since the value of n can reach several hundreds for advanced analog integrated devices, we have studied a heuristic algorithm that considers combinations of subsets of the overall test set. These subsets are easier to model and to order and a heuristic approach is used to form an overall order. This test ordering approach is evaluated for different artificial and experimental case-studies, including a fully differential operational amplifier. These case-studies are simple enough so that it is possible to compare the results obtained with the algorithm with an expected reference order.

The reduction of analog/RF production test costs calls for the optimization of specification-based tests or their replacement by low-cost ones. A variety of techniques have been proposed in recent years, such as specification-based test ordering and compaction, alternate test to predict the specified performances from simpler measurements, and on-chip circuitry to monitor IC performance while alleviating the complexity of test equipment. Since statistical evidence about test quality can only be gathered from large volume production test data, most innovative test techniques fail to gain acceptance for real products. This is because by the time this evidence could be obtained, most test costs would have already been engaged. At this stage, the change of the test procedure would hardly be acceptable and the modification of the design is no longer possible.

This paper discusses the generation of information-rich, arbitrarily-large synthetic data sets which can be used to (a) efficiently learn tests that correlate a set of low-cost measurements to a set of device performances and (b) grade such tests with parts per million (PPM) accuracy. This is achieved by sampling a non-parametric estimate of the joint probability density function of measurements and performances. Our case study is an ultra-high frequency receiver front-end and the focus of the paper is to learn the mapping between a low-cost test measurement pattern and a single pass/fail test decision which reflects compliance to all performances. The small fraction of devices for which such a test decision is prone to error are identified and retested through standard specification-based test. The mapping can be set to explore thoroughly the tradeoff between test escapes, yield loss, and percentage of retested devices.

Alternate RF testing is a very promising candidate for replacing the costly standard specification-based approach. The defect filter in the alternate test flow is a crucial preparatory step for the overall success of alternate test. In this paper, we present a novel nonlinear defect filter based on an estimate of the joint probability density function of the alternate measurements. The construction of the filter does not require a defect dictionary and can accommodate any underlying density without needing any prior knowledge regarding its parametric form.

In this paper we propose a method for evaluating test measurements for complex circuits that are difficult to simulate. The evaluation aims at estimating test metrics, such as parametric test escape and yield loss, with parts per million (ppm) accuracy. To achieve this, the method combines behavioral modeling, density estimation, and regression. The method is demonstrated for a previously proposed Built-In Self-Test (BIST) technique for ΣΔ Analog-to-Digital Converters (ADC) explaining in detail the derivation of a behavioral model that captures the main nonidealities in the circuit. The estimated test metrics are further analyzed in order to uncover trends in a large device sample that explain the source of erroneous test decisions.

In this paper we present the experimental evaluation of a built-in-self-test (BIST) principle for the detection of defective pixels of a CMOS imager. The pixel BIST technique aims at an structural test based on electrical stimuli. Simple electrical test measures are considered. Test limits are set in order to minimize pixel false acceptance and false rejection under mismatch deviations. The pixel BIST is next evaluated by considering the fault coverage obtained with catastrophic and single parametric faults. Finally, test metrics obtained by simulation for mismatch deviations are compared with experimental data.

We present a method that is capable of handling process variations to evaluate analog/RF test measurements at the design stage. The method can readily be used to estimate test metrics, such as parametric test escape and yield loss, with parts per million accuracy, and to fix test limits that satisfy specific tradeoffs between test metrics of interest. Furthermore, it provides a general framework to compare alternative test solutions that are continuously being proposed toward reducing the high cost of specification-based tests. The key idea of the method is to build a statistical model of the circuit under test and the test measurements using nonparametric density estimation. Thereafter, the statistical model can be simulated very fast to generate an arbitrarily large volume of new data. The method is demonstrated for a previously proposed built-in self-test measurement for low-noise amplifiers. The result indicates that the new synthetic data have the exact same structure of data generated by a computationally intensive brute-force Monte Carlo circuit simulation.

We present a general method to evaluate RF built- in self-test (BIST) techniques during the design stage. In particular, the adaptive kernel estimator is used to construct an estimate of the joint probability density function of the performances of the RF device under test and the actual BIST measurements. The density is sampled to generate a large volume of new data, which is subsequently used to estimate the relevant test metrics with parts per million (ppm) accuracy given the BIST limits. Thus, the BIST limits can be set to obtain the desired trade-offs between different test metrics. The proposed method aims to assist designers in comparing RF BIST techniques on the basis of accurately calculated test metrics and to provide information for early BIST refinements, thus reducing the design cycles. The method is demonstrated for a previously published RF BIST technique applied to an LNA.

There is an increasing demand for test and diagnosis expertise in the global semiconductor industry, in sectors ranging from foundries to test houses, to IDM companies, and from fabless design houses to EDA companies. Test education, however remains a niche, highly specialized subject area in the graduate curriculum and is seldom covered in undergraduate classes. In this panel, we evaluate the current health of academic test education and debate the role and goals of future test education, as well as those changes that need to be made to meet the global market demands.

This paper evaluates a new Built-In-Self-Test (BIST) technique for CMOS imagers. The test stimuli are based on applying electrical pulses at the pixel photodiode anode in order to carry out a purely electrical test. The aim of this work is to eliminate some, if not all, optical tests of the pixel matrix to reduce time and cost during production testing at a wafer level. The quality of the BIST technique is evaluated by computing test metrics such as fault coverage for catastrophic and single parametric faults, and pixel fault acceptance and fault rejection under process deviations for two different pixel architectures.

For design-for-test (DFT) purposes, analogue and mixed-signal testing has to cope with the difficulty of test evaluation before production. This paper aims at evaluating test measures for RF components in order to optimize production test sets and thus reduce test cost. For this, we have first developed a statistical model of the performances and possible test measures of the circuit under test (a low noise amplifier). The statistical multi-normal model is derived from data obtained using Monte-Carlo circuit simulation (five hundred iterations). This statistical model is then used to generate a larger circuit population (one million instances) from which test metrics can be estimated with ppm precision at the design stage, considering just process deviations. With the use of this model, a trade-off between defect level and yield loss resulting from process deviations is used to set test limits. After fixing test limits, we have carried out a fault simulation campaign to verify the suitability of the different test measurements, targeting both catastrophic and single parametric faults. Catastrophic faults are modelled by shorts and opens. A parametric fault is defined as the minimum value of a physical parameter that causes a specification to be violated. Test metrics are then evaluated for the LNA case-study. As a result, test metrics for functional measurements such as S-parameters and noise figure are compared with low cost test measurements such as RMS and peak-to-peak current consumption and output voltage, input/output impedance, and the correlation between current consumption and output voltage

This paper introduces a new method combining low frequency actuation signal as test stimuli and envelope detection on the RF (radiofrequency) output signal to provide a low cost mean for offline as well as for online testing of RF MEMS switches. The study includes the modelling of RF MEMS switches as well as some ideas how to test online and diagnose their functionality. The proposed approach uses the principle of alternate test that replaces conventional specification-based testing procedures, which require sophisticated test equipment and are time consuming. The basic idea is to use the actuation signal as a low frequency online test stimuli to the RF device. The low frequency characteristics measured from the envelope of component response are utilized in a regression process to predict the RF conventional specifications parameters like s-parameters. In the context of our online testing scheme, on and off transition time estimated from the output low frequency envelope are used as test metrics and are concurrently updated using recursive algorithms. Preliminary validation results obtained on a capacitive RF switch are very encouraging.

In this paper we present a new architecture for audio analog-to-digital converters (ADCs) that includes a Built-in Self-Test (BIST) technique for the test of the signal-to-noise and distortion ratio (SNDR). A periodical binary stream is generated in the chip in order to stimulate the converter. The reuse of the bandgap circuit already existing in the converter allows us to generate the test stimulus with a very small analog area overhead. The output response analysis is performed by means of a sine-wave fitting algorithm. The reuse of the digital filter already existing in the converter allows us to generate a synchronized reference signal necessary for the fitting algorithm. The BIST technique is equivalent to a standard test carried out with a sinusoidal signal at -12 decibels Full-Scale (dBFS). The total test time is 60 ms and the estimated BIST overhead area is 7.5% of the whole stereo converter area in a 0.13 mum CMOS technology. Experimental results show that the correlation between the embedded self-test and a sinusoidal standard test is excellent, with a SNDR error smaller than 1 dB.

Pseudorandom test techniques are widely used for measuring the impulse response (IR) for linear devices and Volterra kernels for nonlinear devices, especially in the acoustics domain. This paper studies the application of pseudorandom functional test techniques to linear and nonlinear MEMS built-in-self-test (BIST). We will first present the classical pseudorandom BIST technique for linear time invariant (LTI) systems which is based on the evaluation of the IR of the device under test (DUT) stimulated by a maximal length sequence (MLS). Then we will introduce a new type of pseudorandom stimuli called the inverse-repeat sequence (IRS) that proves better immunity to noise and distortion than MLS. Next, we will illustrate the application of these techniques for weakly nonlinear, purely nonlinear and strongly nonlinear devices

This paper introduces a computer-aided-test platform that has been developed for the evaluation of test techniques for analogue and mixed-signal circuits. The CAT platform, integrated in the Cadence design framework environment, includes tools for fault simulation, test generation and test optimization for these types of circuits. Fault modeling and fault injection are simulator independent, which makes this approach flexible with respect to past approaches. In this paper, the use of this platform is illustrated for test optimization for the case of a fully differential amplifier. Test limits are set using a statistical circuit performance analysis that accounts for process deviations. Test metrics are estimated using this analysis. Specification-based tests are next optimized in terms of their capability of detecting catastrophic faults

The production test of CMOS image sensors is complicated and expensive as an electrical and an optical test must be executed for the pixel matrix. In this paper we study a built-in-self-test (BIST) technique for the pixels. The technique is based on applying a voltage stimulus at the photosensitive element of the image sensor. The aim of this work is to avoid light stimuli to realise an only electrical test to determine if a pixel is functional or not. This will then reduce test time and test cost. To quantify the quality of this test approach, test metrics such as fault rejection and fault acceptance are estimated. Catastrophic and parametric faults are taken into consideration for the estimation of the test quality

The test of high resolution sigma-delta analogue-to-digital converters (SigmaDelta ADCs) is a costly task due to its high resolution and the large number of samples required. In this paper, we propose a built-in self-test (BIST) technique for the test of SNDR (signal-to-noise plus distortion ratio) in SigmaDelta ADCs. The technique, mostly digital, uses a binary stream as test stimulus and carries out a sine-wave fitting algorithm to analyse the output response. Both the test signal generation and the output response analysis are performed on-chip, taking advantage of the digital resources already present in a SigmaDelta ADC. Simulations results show the capability of this technique to obtain measures of the SNDR for a 16-bit audio SigmaDelta ADC

This paper is aimed at studying defect-oriented test techniques for RF components in order to optimize production test sets. This study is mandatory for the definition of an efficient test flow strategy. We have carried out a fault simulation campaign for a low-noise amplifier (LNA) for reducing a test set while maintaining high fault coverage. The set of production test measurements should include low-cost structural tests such as simple current consumption and only a few more sophisticated tests, dedicated to functional specifications, such as S parameters, noise figure (NF) or IP3.

Microsystems are usually affected by multiple failure sources. A faulty behavior caused by different types of defects and failure sources can exhibit small functional errors that are difficult to detect using structural testing. From here stems the necessity to apply specification-based functional testing on the basis of a method that carries enough information about the physical behavior of the device under test (DUT). Such a method can be attained by the impulse response (IR) measurement of the linear DUT. In this paper we explain three existing techniques to measure the IR of linear time-invariant (LTI) devices. Weak nonlinearities that can be caused by system nonidealities and measurement distortions are considered. Only simple techniques that do not require the presence of a digital signal processor (DSP) on-chip are considered. A detailed comparison between these techniques is carried out to demonstrate our choice for a BIST (built-in self-test) approach.

The test of analogue and mixed-signal (AMS) cores requires the use of expensive AMS testers and accessibility to internal analogue nodes. The test cost can be considerably reduced by the use of built-in-self-test (BIST) techniques. One of these techniques consists of generating analogue test signals from digital test patterns (obtained via /spl Sigma//spl Delta/ modulation) and converting the responses of the analogue modules into digital signatures that are compared with the expected ones. This paper presents an implementation of the analogue test signal generation part that includes programmability of the circuit blocks, leading to an improvement of performance and a reduction of circuit size with respect to previous approaches. A 0.18 /spl mu/m CMOS circuit has been designed and fabricated, allowing the generation of test signals ranging from 10 Hz to 1 MHz.

This paper presents a Built-In-Self-Test (BIST) implementation of pseudo-random testing for Micro Electro-Mechanical Systems (MEMS). The technique is based on Impulse Response (IR) evaluation using Maximum-Length Sequences (MLS). We will demonstrate the use of this technique and move forward to find the signature that is defined as the necessary samples of the impulse response needed to carry out an efficient test. We will use Monte-Carlo simulations to find the set of all fault-free devices under test (DUT). This set defines the impulse response space and the signature space. A DUT will be judged fault-free according to its signature being inside or outside the boundaries of the signature space. Finally, the test quality will be evaluated as function of the probabilities of false acceptance and false rejection, yield and percentage of test escapes. According to these test metrics, the design parameters (length of the MLS and the precision of the analogue to digital converter ADC) will be derived.

This paper presents a memory-based on-chip analogue test signal generation approach that is suitable for the test of an Analogue and Mixed-Signal (AMS) core. This core contains programmable electronic interfaces for acoustic and ultrasound transducers. The test signals that must be generated on-chip have only low or moderate frequencies (10 Hz-10 MHz). The test circuitry designed in a 0.18 μm CMOS technology includes a programmable shift-register, a clock divider, and a programmable switched-capacitor filter bank. By controlling the shift-register length and the sampling frequency, the paper shows that high quality single tone signals can be generated on chip in the band of interest.

This paper presents an implementation of on-line testing techniques for the case of a decimation filter. The decimation filter is used in a /spl Sigma//spl Delta/ analogue-to-digital converter that is in turn used in a built-in-self-test (BIST) circuitry for mixed-signal core testing. Thus, the filter itself must be self-testable. Three different one-line self-test techniques are studied and compared for a 0.18 /spl mu/m CMOS technology. The first one uses a non-concurrent structural test technique and the others are both based on semi-concurrent test methodologies. In all cases, the on-line test circuitry is automatically synthesized and exploits the idle time of the functional units to apply either a structural or a functional test.

Recent developments in the field of MEMS indicate a clear move toward systems, rather than just individual components. Design and fabrication of these components include new methods and techniques. Does testing require new methodologies and tools ? Will we be able to include MEMS in the SoCs flow ?

A major problem for applying self-test techniques to MEMS is the multi-domain nature of the sensing parts that require special test equipment for stimuli generation. In this work we describe, for three different types of MEMS that work in different energy domains, how the required nonelectrical test stimuli can be induced onchip by means of electrical signals. This provides the basis for adding BIST strategies for MEMS parts embedded in the coming generation of integrated systems. The first case corresponds to an accelerometer as a review of a classical example. The last two cases correspond to piezoresistive and infrared sensors that we use in innovative applications under development in our Laboratory, and for which the self-test methods are new to our knowledge. The last case is also illustrated as a complete application that corresponds to an infrared imager. The on-chip test signal generation proposed requires only slight modifications and allows production test of the imager with a standard test equipment, without the need of special infrared sources and the associated optical equipment. The test function can also be activated off-line in the field for validation and maintenance purposes.

This paper illustrates an approach to design and validation of heterogeneous systems. The emphasis is placed on devices which incorporate MEMS parts in either a single mixed-technology (CMOS + micromachining) SOC device, or alternatively as a hybrid system with the MEMS part in a separate chip. The design flow is general, and it is illustrated for the case of applications embedding CMOS sensors. In particular, applications based on finger-print recognition are considered since a rich variety of sensors and data processing algorithms can be considered. A high level multi-language/multi-engine approach is used for system specification and co-simulation. This also allows for an initial high-level architecture exploration, according to performance and cost requirements imposed by the target application. Thermal simulation of the overall device, including packaging, is also considered since this can have a significant impact in sensor performance. From the selected system specification, the actual architecture is finally generated via a multi-language co-design approach which can result in both hardware and software parts. The hardware parts are composed of available IP cores. For the case of a single chip implementation, the most important issue of embedded-core-based testing is briefly considered, and current techniques are adapted for testing the embedded cores in the SOC devices discussed.

A design methodology for on-line testing analog linear fully differential (FD) circuits is presented in this work. The test strategy is based on concurrently monitoring via an analog checker the common mode (Chi) at the inputs of all amplifiers, The totally self-checking (TSC) goal is achieved for linear FD implementations provided that the checker CM threshold is small enough with respect to the specified margins of erroneous behavior in the circuit outputs. The design methodology is illustrated for a switched-capacitor biquadratic filter and the self-checking properties evaluated for a hard/soft-fault model. A large checker threshold of 100 mV of CM is chosen since the filter implementation does not minimize nonidealities (e.g., amplifier offsets or clock feedthrough) which result in significant CM components. The circuit outputs are accepted to deviate within a 10% band. With the implemented checker, the TSC goal is not achieved for some faults in narrow regions of the frequency band. For the worst case, a hard fault which results in a 31% deviation is undetected in only a narrow band of approximately 310 Hz. The circuit can be made TSC with a checker threshold of 40 mV and an accepted output deviation of 15%. This is, however, more demanding on the checker (which currently takes less than 3% of the total area and about 7.6% of the total power) and requires an improved filter implementation to reduce CM components. Our solution consists of relaxing a bit the TSC property of the functional block and applying a periodical off-line test to make the checker strongly code disjoint (SCD). This is easy to implement since an off-line test is also required for the checker. The checker outputs a double-rail error indication which ensures compatibility with digital checkers and makes the design of self-checking mixed signal circuits straightforward. The circuit-level mixed-signal approach is extended to the board level by means of the IEEE Std. 1149.1 digital test bus.

As next generation chips embedding MEMS appear, fault-based and defect-oriented tests for MEMS parts become important for cost-effective production testing. This paper presents realistic fault modeling and simulation techniques for suspended thermal MEMS, an already successful domain of application.

An approach to test optimization in switched-capacitor systems based on fault simulation at switch-level is presented in this paper. The advantage of fault simulation at this granularity level is that it facilitates test integration as early as possible in the design of these systems. Due to their mixed-signal nature, both catastrophic and parametric faults must indeed be considered for test optimization. Adequate switch-level fault models are presented. Test stimuli and test measures can be selected as a function of fault coverage. The impact of design parameters such as switch resistance on fault coverage is studied and design parts of poor testability are located.

Silicon-compatible micromachining provides a low cost monolithic solution for the integration of microelectromechanical systems (MEMS). In the last years, CMP (the French MultiProject Wafer Service) has made available technological solutions for the fabrication of CMOS-compatible MEMS. Numerous monolithic devices have been fabricated using this service. The inspection of failed devices has allowed the identification of the most typical failure mechanisms and design errors for this type of MEMS. This valuable information, together with a detailed analysis of the fabrication processes, is used in this paper to provide a classification of faults in silicon-compatible MEMS which can later be used for fault simulation and testing.

A tool for the switch-level fault simulation and test evaluationof switched-capacitor systems is presented. Time or frequency-domainfault simulations with SWITCAP and time-domain faultsimulations with HSPICE can be performed. Adequate fault modelsare presented for both simulators. The tool has proven to bevery useful in the early evaluation of test strategies, providing similarresults to those obtained at the transistor-level.

This paper presents a novel multifunctional test structure called Analog BulLt-in Block Observer (ABILBO). This structure is based on analog integrators and achieves analog scan, test frequency generation and test response compaction. A high fault coverage was obtained by using a discrete switched-capacitor ABILBO for testing a biquad filter. The ABILBO area overhead and performance penalty can be very low if functional and testing circuitry are shared. This is typically the case of high order filters based on a cascade of biquads.

The design of checkers aimed at the concurrent test of analog and mixed-signal circuits is considered in this paper. These checkers can on-line test duplicated and fully differential analog circuits. The test approach is based on exploiting the inherent redundancy of these circuits which results in the use of a code for the analog signals. The analog code is monitored by the checkers. An error signal which complies with existing digital self-checking parts is generated in the case that a code fails out of the valid code space. For the verification of the analog codes, absolute tolerance margins and tolerance margins which are made relative to signal amplitude are considered. A test pattern generator for off-line testing of the checkers is proposed.>

An approach to the test and diagnosis of fully dif-ferential analogue circuits is described in this paper. The test approach is based on o-line monitoring via an analogue BIST observer the inputs of the opera-tional ampliers in the circuit. The analogue BIST can detect both hard and soft faults. Diagnosis resolu-tion is improved by also monitoring the outputs of the operational ampliers. Faulty components can then be located and the actual defective value of a faulty pas-sive component determined. 1