In this paper we report on a wireless Ethernet link over 60GHz mmWave, which is a full-duplex wireless link in the same frequency channel. To provide a dense wireless network, beam forming with a phased-array transceiver is a key technology for frequency reuse. We introduced a particle swarm optimization algorithm for beam forming with effective interference cancellation in each field. This method works independent of the transceiver arrangement and is free from device-specific variability and non-linearity. We prototyped the wireless Ethernet link system and achieved a BER less than 1.0E-11 at a 3m distance. We were able to prove its feasibility at system-level application.

This paper describes a millimeter wave wireless system using the 60-GHz frequency band, focusing on the data recovery algorithm and implementation to compensate for both the phase noise and the DC offset. Our robust baseband system supports data transfers at 7.04 Gbps using 16-QAM single-carrier with effective digital compensation, an improved adaptive equalizer, and a post-phase rotator and post-shifter. We use a low-overhead frame format without training symbols in the payload and RS(255, 239) as the error correction code so that we can retain spectral efficiency with an effective data rate around 6.6 Gbps with a bit error rate of 4.0E-5 at 3 m distance. Our results show how millimeter wave technology can provide higher data rates and higher aggregated channel capacities for future dense networks.

This paper presents a high-speed multimedia content-downloading system using 60GHz millimeter wave (mmWave) technology. For a cost-effective solution, the system makes use of conventional 802.11 for the interactive controls between an access point and smart mobile devices, handling such services as access point discovery, authentication, mmWave link establishment, beam steering, and lost packet recovery. The high-speed one-way mmWave link is dedicated to the transfer of content data. The smart mobile device only has an mmWave receiver so that it can keep its power dissipation and hardware costs low. The content data is downloaded from an access point to such a smart mobile device via an external storage component of the mobile device. To use the high bandwidth of the mmWave, the mmWave receiver writes directly to the external storage as a wireless attached memory, which is accessed by the smart mobile device via its SD interface. We built a proof-of-concept prototype with a smartphone receiving data from an mmWave system, and evaluated the performance.

This paper deals with mm Wave MIMO link design strategy for wireless data center applications where the MIMO degrees of freedom is taken into account in multi-node packet networking environments. The problem is treated differently from the coordinated multiuser MIMO situation and the link design is optimized independently in each node with meeting control and data plane requirements for contention-based packet switching. In particular, we propose using an interference-aligned out-of-band control plane to improve the unidirectional bonded in-band data plane collision-related performance degradation with a limited number of antenna elements per node. We also present a high-level implementation plan.

This paper presents a cost-effective high-speed multimedia-content download system using a hybrid wireless link consisting of a 60-GHz (mmWave) link and a conventional wireless link, such as IEEE 802.11. The capability gap between the components of existing systems and a mmWave link caps system-level performance and degrades resource utilization. We developed an FPGA-based prototype system to investigate system-level performance for well balanced systems. Our performance evaluation involved changing the PHY parameters, data acknowledgement (ACK) methods and link quality. Under the point-to-point network, our results confirmed that a hybrid system with a unidirectional mmWave link using software burst ACK and well optimized packet and burst sizes can achieve competitive performance.

This paper presents a new type of wireless networking applications in data centers using steered-beam mmWave links. By taking advantage of clean LOS channels on top of server racks, robust wireless packet-switching network can be built. The transmission latency can be reduced by flexibly bridging adjacent rows of racks wirelessly without using long cables and multiple switches. Eliminating cables and switches also reduces equipment costs as well as server installation and reconfiguration costs. Security can be physically enhanced with controlled directivity and negligible wall penetration. The aggregate data transmission BW per given volume is expected to scale as the fourth power of carrier frequency. The paper also deals with the architecture of such network configurations and a preliminary demonstration system.

This paper proposes a hardware design debugging method, transition and transaction tracer (TTT), which probes and records the signals of interest for a long time, hours, days, or even weeks, without a break. It compresses the captured data in real time and stores it in a state transition format in memory. It can be programmed to generate a trigger for a logic analyzer when it detects certain transitions. The visualizer, which shows the captured data in the matrix, timing-chart, and state-transition diagram formats, helps the engineer effectively find bugs.

In System on Chip (SoC) design, growing design complexity has forced designers to start designs at higher abstraction levels. This paper proposes an SoC design methodology that makes full use of FPGA capabilities. Design modules in different abstraction levels are all combined and run together in an FPGA prototyping system that fully emulates the target SoC. The higher abstraction level design modules run on microprocessors embedded in the FPGAs, while lower-level synthesizable RTL design modules are directly mapped onto FPGA reconfigurable cells. We made a hardware wrapper that gets the embedded microprocessors to interface with the fully synthesized modules through IBM CoreConnect buses. Using this methodology, we developed an image processor SoC with cryptographic functions, and we verified the design by running real firmware and application programs. For the designs that are too large to be fit into an FPGA, dynamic reconfiguration method is used.

We propose an elliptic curve (EC) cryptographic processor architecture that can support Galois fields GF(p) and GF(2/sup n/) for arbitrary prime numbers and irreducible polynomials by introducing a dual field multiplier. A Montgomery multiplier with an optimized data bus and an on-the-fly redundant binary converter boost the throughput of the EC scalar multiplication. All popular cryptographic functions such as DSA, EC-DSA, RSA, CRT, and prime generation are also supported. All commands are organized in a hierarchical structure according to their complexity. Our processor has high scalability and flexibility between speed, hardware area, and operand size. In the hardware evaluation using a 0.13-/spl mu/m CMOS standard cell library, the high-speed design using 117.5 Kgates with a 64-bit multiplier achieved operation times of 1.21 ms and 0.19 ms for a 160-bit EC scalar multiplication in GF(p) and GF(2/sup n/), respectively. A compact version with an 8-bit multiplier requires only 28.3 K gates and executes the operations in 7.47 ms and 2.79 ms. Not only 160-bit operations, but any bit length can be supported by any hardware configuration so long as the memory capacity is sufficient.