Energy-efficient task allocation and scheduling schemes with deterministic fault-tolerance capabilities are proposed for symmetric multiprocessor systems executing tasks with hard real-time constraints. The proposed heuristic is proven to achieve energy savings by optimally balancing application workload among processors in a system. Based on the observation that fault-free operation is expected to remain dominant in the near future and the probability of the worst case faults is low, an optimistic fault-tolerant heuristic is then proposed to achieve maximum energy savings in the absence of faults while degrading gradually to meet application timing requirements in the worst case of faults. Simulation results show that compared to state-of-art allocation and scheduling schemes proposed heuristic achieves average energy savings of up to 70%. It is also shown that optimistic approach is more resilient to variations in application utilizations and fault occurrences beyond system specifications.

Errors introduced by radiation-induced single event upset and single event latchup in very deep submicron (VDSM) ICs necessitate concurrent error detection (CED) and correction. Power consumed by circuits used for detecting and correcting errors becomes an extra burden on the tight power budget of VDSM ICs. The triple-modular redundancy-based fault tolerance technique, which is traditionally used for error detection and correction, incurs over 200 percent power overhead. In this paper, we propose register-transfer level low-power on-demand error correction techniques. Proposed techniques implement an original computation and a recomputation in datapath and compare the results from two computations to monitor the health of circuit. A mismatch in results indicates faulty computation and a second recomputation is triggered to rectify the error. The proposed techniques can detect and correct SEU induced transient errors and detect SEL induced permanent errors with as little as 12 percent power overhead

In this paper we investigate fault tolerance and Dynamic Voltage Scaling (DVS) in hard real time systems. We present two low-complexity fault-aware scheduling algorithms that combine feasibility analysis of Rate Monotonic Algorithm (RMA) schedules and DVS-based frequency scaling using exact characterization of RMA algorithm. These algorithms lay the foundation for highly efficient online schemes that minimize energy consumption by adapting DVS policies to runtime behavior of tasks and fault occurrences without violating the offline feasibility analysis. Simulation results demonstrate energy savings of up to 60% over low-energy offline scheduling algorithms [22].

Security protocols use session negotiation protocols for establishing and managing secure sessions and secure data exchange protocols for secure data communications. Deployment of resource-intensive security protocols in battery-powered mobile devices has elevated energy characteristics to an important design metric. In this paper we study the energy consumption characteristics of secure session negotiation protocols within the framework of Internet security protocol (IPSec). Based on the observations made we present techniques to optimize the energy consumed by session negotiation protocols. Proposed techniques achieve 5x to 11x energy savings without compromising the session security. We show that the proposed techniques are platform independent and discuss the impact of platform specific characteristics, such as available system resources, on the energy characteristics of the system.

In this paper, we extend OPNET/spl reg/ network simulator wireless local area network (WLAN) models to incorporate energy and security. We then use these models to study (1) performance and energy characteristics of large-scale secure WLAN networks under varying channel conditions and (2) impact of energy-efficient security protocol adaptations proposed in [(R. Karri and P. Mishra, 2003), (R. Karri and P. Mishra, 2002)] on the energy consumed by Internet security protocol (IPSec).

We investigate techniques to minimize the energy consumed by a secure wireless session without compromising the security of the session. While we have shown elsewhere (see Karri, R. and Mishra, P., submitted to ACM MOBIHOC 2002; http://emme.poly.edu/Goodies/TEMP/MOBIHOC2002.pdf) that the energy consumed by a secure session is reduced by compressing the session negotiation messages, the protocol header and the data, we now show that it is important to match the block size of compression to the data cache size of the device. We also investigate the choice of a bulk encryption algorithm (3DES vs. AES) and a key exchange protocol (Diffie-Hellman vs. RSA) based on the energy consumed by a secure wireless session. These techniques yield energy savings of 1.3/spl times/ during data transmission and 1.2/spl times/ during data reception beyond those obtained by techniques given in our cited paper. These techniques complement and supplement those proposed in that paper, and when combined, yield overall energy savings of 2.1/spl times/ during data transmission and 4.35/spl times/ during data reception.

Fault-based side-channel cryptanalysis is very effective against symmetric and asymmetric encryption algorithms. Although straightforward hardware and time redundancy-based concurrent error detection (CED) architectures can be used to thwart such attacks, they entail significant overheads (either area or performance). The authors investigate systematic approaches to low-cost low-latency CED techniques for symmetric encryption algorithms based on inverse relationships that exist between encryption and decryption at algorithm level, round level, and operation level and develop CED architectures that explore tradeoffs among area overhead, performance penalty, and fault detection latency. The proposed techniques have been validated on FPGA implementations of Advanced Encryption Standard (AES) finalist 128-bit symmetric encryption algorithms.

Fault-based side channel cryptanalysis is very effective against symmetric and asymmetric encryption algorithms. Although straightforward hardware and time redundancy based concurrent error detection (CED) architectures can be used to thwart such attacks, they entail significant overhead (either area or performance). In this paper we investigate systematic approaches to low-cost, low-latency CED for symmetric encryption algorithms based on the inverse relationship that exists between encryption and decryption at algorithm level, round level and operation level and develop CED architectures that explore the trade-off between area overhead, performance penalty and error detection latency. The proposed techniques have been validated on FPGA implementations of AES finalist 128-bit symmetric encryption algorithms.