Internet of Things (IoT) architecture regulates the compositions and their relationships, which is the core factor determining the performance of IoT. With the development of IoT applications, the types and quantities of devices that need to be integrated are increasing, and the functional requirements are also diverse, thus IoT becomes complex system. However, the existing coarse-grained and single-dimensional IoT architecture is not conducive to accurately model the complex IoT system and brings difficulties to the effective system design. Therefore, considering the energy conversion of each physical entity in the interaction process of IoT, we reasonably think that this energy conversion is displayed through the information system function, and thus find that IoT has three attributes (physics, information, and function). We further design the physical subarchitecture, the information subarchitecture, and the functional subarchitecture. The functional subarchitecture is the external performance of the operation of the information subarchitecture on the physical subarchitecture. On the basis of three subarchitectures, six closed-loop information operation modes have been designed to comprehensively express the working mechanism of IoT in detail. Three subarchitectures constitute the physical-information-functional architecture (also known as five-domains and three-systems architecture) for IoT. The performance evaluation using eight classic IoT architecture indicators shows that the proposed architecture exceeds the existing ones. Finally, by applying the architecture, we have also successfully developed a smart factory industrial IoT as a national intelligent manufacturing demonstration factory.

Techniques for the foreground calibration of split capacitor successive approximation register (SAR) are discussed. The used methods of digital calibration requires a digital post-processing that can be a limit for the resulting overhead. The presented techniques allow directly obtaining the digital output. Two methods address the mismatch among the unit elements in the most significant byte (MSB) segment and the mismatch at the MSB-LSB interface. A 16-bit SAR ADC with a sampling rate of 1MS/s employs both calibration techniques and verifies the methods. The simulation results show a Schreier merit of 166.3 dB, a signal-to-noise-and-distortion ratio (SNDR) of 87 dB, and an SFDR of -100 dB. A chip fabricated in a 180-nm Bipolar-CMOS-DMOS (BCD) process almost obtains the expected SNDR. The experimental result shows that the spurious-free dynamic range (SFDR) improves from 70.71 to 93.29 dB.

This work presents the design of a bipolar junction transistor (BJT)-based temperature sensor with a sigma-delta analog-to-digital converter ($\Sigma \Delta $ADC) fabricated in a 0.6$\mu $m BiCMOS process. The sensor utilizes a proportional to absolute temperature (PTAT) current source embedding an auto-zeroing amplifier to bias the BJT core while effectively reducing offset errors. Additionally, this work achieves the combination of the temperature-sensing BJT core and the$\Sigma \Delta $modulator, utilizing dynamic element matching (DEM) technique to accurately generate three different ratios (1:9, 9:1, 5:5) of BJT bias currents to cooperate with the modulator for modulation. The innovative modulation method in this work can reduce the errors caused by the operational amplifier offset voltage and BJT mismatch, completing the digitization of temperature without the need for a reference voltage source. Moreover, the sensor integrates a complete digital signal processor (DSP), allowing on-chip calibration by adjusting the operating cycle of the modulator and the initial value of the counter to obtain accurate and directly readable temperature data. It operates under a 3.3 V supply within a temperature range from −50 °C to 125 °C. Lastly, it achieves a 17 mK resolution and an inaccuracy of ±1.5 °C (3$\sigma $) after an on-chip single-point calibration.

The goal of new engineering is to cultivate innovative talents who can adapt to the requirements of new era and new technology. Under the background of new engineering, the construction of “Double First-Class” initiative puts forward higher requirements for the basic theory of integrated circuit teaching and research. This paper explores reform methods in the teaching content, teaching mode and practical teaching of integrated circuit related courses in accordance with the talent training mode of innovative application-oriented undergraduate education. The purpose of this education reform is to cultivate the students' ability to think independently and solve practical problems. At the same time, it can promote the communication between electronic specialty and other majors, and cultivate students' comprehensive quality and innovation ability.

A discrepancy of monolithic microwave-integrated circuit (MMIC) amplifier simulations is discussed for conventional electromagnetic (EM) circuit co-simulation in advanced design system (ADS). An obvious discrepancy occurs when microstrip (MS) type transistor schematic models are used in a high gain MMIC amplifier. The coupling effect of a backside via hole in the MS-type model, which is excluded from EM layout simulation, is demonstrated to be the root of this error that will become significant in high-gain MMIC amplifier design. A new method is proposed to include a source via hole of the MS-type transistor in MMIC layout EM simulations. Simulation experiments confirm that this new method can significantly improve the EM simulation accuracy when including a transistor source via hole in the circuit layout EM simulation. The intercoupling effect of the transistor source via is investigated on the correlation with frequency, current gain, via separation distance, and substrate thickness.

The purpose of educational innovation is to train talents meeting the needs of modern science and technology development and to promote the sound and fast development of society. In this paper, the present situation and existing problems of engineering education personnel training are discussed, and the teaching method of integrating theory and practice is put forward. At the same time, students are encouraged to participate in the base practice opportunities provided by enterprises to promote the development of students' theoretical knowledge and practical skills in all aspects.

In recent years, the educational innovation of electronic information courses has attracted widespread attention. This article combines the emergence of new educational concepts and teaching methods to propose a four-in-one educational method of “theory-simulation-experiment-innovation”. Practical teaching proves that the four-in-one teaching method helps to improve the teaching quality of electronic circuits.

Current image compression algorithms based on transforms can achieve ideal performance for natural images, but do not do well with synthetic aperture radar (SAR) images. We propose a learned compression framework with pyramidal features and quality enhancement to fully exploit the redundancy among image pixels and to improve the compression bitrate and reconstruction quality. Based on the variational autoencoder (VAE) architecture, pyramidal decomposition is performed at the first autoencoder to extract both global and coarse feature maps. The latent distribution is modeled by the second hyperprior autoencoder with a single-Gaussian model for more accurate and flexible entropy estimation. Universal quantization is applied to consolidate the entropy estimation accuracy of the hyperprior network. To further improve reconstruction quality, a residual dense network (RDN) is adopted to fully capture local and global features. Experimental results demonstrate that the proposed framework provides a better rate-distortion tradeoff than standard codecs such as JPEG, JPEG2000, and learning-based methods on both the Sandia and ICEYE datasets.

Given the uniqueness of synthetic aperture radar (SAR) images, traditional optical image compression algorithms cannot fully exploit their redundant information. To improve SAR image compression in terms of rate–distortion performance and visual perception, an end-to-end SAR image compression convolutional neural network (CNN) model based on a variational autoencoder is proposed. The proposed CNN model consists of a main autoencoder and a hyper autoencoder. To reduce dependencies in latent space, a joint transform of linear CNN and nonlinear generalized divisive normalization (GDN) activation is applied in the main autoencoder. Moreover, residual blocks are combined with the transforms to boost the efficiency of feature learning and make use of subpixels to improve the quality of reconstructed images. Instead of a fixed entropy model, a conditioned entropy model that works with a hyperprior network is used to learn the distribution of latents, which helps to further improve the compression quality. During training, the model is optimized by evaluating the rate–distortion performance. The experimental results show that the proposed method can achieve better distortion performance than JPEG, JPEG2000, and the available CNN-based method in terms of objective evaluation criteria and human vision perception quality.

With the increasing complexity of modern design, mixed-cell-height designs have become more popular, which makes the legalization problem more challenging. In this article, a robust negotiation-based legalizer (NBLG) is proposed to reduce average displacement and maximum displacement for mixed-cell-height circuits with considering the fence region and technology constraints. By dissecting the main components of the negotiation-based method, we divide the placement grid in terms of placement sites and reformulate the legalization problem as a resource allocation task. We then allow all movable cells to gradually remove overlaps in a surrounding window with two individual techniques: 1) isolation point and 2) adaptive penalty function. We also adopt a deterministic multithreading technique to accelerate the convergence of our algorithm. Experimental results show that our legalizer achieved the minimal average displacement and maximum displacement in a reasonable runtime compared with state-of-the-art methods.

In the teaching of electronic engineering, some practical projects need to be added in order to connect various courses together. To strengthen the connections between courses, the project-based teaching method proposed in this paper advocates linking the knowledge of different courses through the combination of theory and practice. With this as a guide, projects have been set up for students. One of them is about designing and making a managed ethernet switch. In the process of making and completing this project, the students' ability has been significantly improved, which fully proves the benefits of the teaching method.

This article puts forward some feasible sensor related courses redesign for solving the current predicament of electronic information course education. Two practical teaching cases have been given in this work. The approach proposed in this work allows students to flexibly use what they have learned, then put theories into practice.

This paper presents a novel method to calibrate the mismatch in the process of analyzing the acquired information by remote sensing technology. Moreover, the essence of reducing mismatch is the correction of analog-to-digital converters (ADCs). The proposed 12-bit successive approximation register (SAR) ADC uses the Vcm-Based structure to reduce the significant power from the most significant bit (MSB), and calibrates the mismatch in the capacitive array through sorting capacitors. The proposed ADC is implemented in the 180nm complementary metal-oxide-semiconductor (CMOS) technology and improves the spurious-free dynamic range (SFDR) from 62.59dB to 78.16dB and the signal-to-noise-distortion ratio (SNDR) from 58.356dB to 70.04dB.

This paper presents a digital magnetic field detection system, which can collect and analyze the remote sensing data by using the analog-to-digital converters (ADCs). The proposed digital magnetic field detection system contains two different types of digital pulse-width modulation (PWM) ADCs by using the complementary metal-oxide-semiconductor (C-MOS) mixed-signal technology and the field-programmable gate array platform (FPGA). The 12-bit digital PWM delta-sigma (ΔΣ) ADC is implemented in 180nm CMOS mixed-signal technology and achieves the signal-to-noise-distortion ratio (SNDR), the spurious free dynamic range (SFDR) and the effective number of bits (ENOB) are 70.68dB, 92.62dB and 11.44-bit with a supply voltage of 1.2V and at a sampling rate of 58.82kS/s. The digital PWM successive approximation register (SAR) ADC is based on FPGA to reduce the interference in the workpiece magnetic field to enhance reliability. Proposed digital PWM ADCs can be combined with a Hall effect sensor to measure the magnitude of a magnetic field without using the microcontroller, which are widely used for proximity sensing, positioning, speed detection, and current sensing applications.

Nowadays, the field of microelectronics has become the drive for the advancement of the times, which promotes new demands on the cultivation of the students in colleges and universities. In order to keep up with the trend of the global engineering educational reform, three important reforms in education have been in progress step by step, including classroom teaching, innovative training and virtual laboratories. At first, for enhancing and integrating the existing courses related to the circuit, so that the students can comprehend the existing knowledge much more effectively, an important and effective curriculum reform has been performed by combining “Circuit Analysis” and “Analog Circuit Foundation” into one course; Then, innovative training has been carried out to cultivate the team skills among the students; Finally, in consideration of the rapid development of the electrical and electronic experiment, the conventional laboratory equipment may not satisfy the demand of every student due to financial constraints, therefore, the construction of virtual simulation experiment center is an efficient way to break this bottleneck. As a result, the atmosphere of academic innovation of the pursuit of truth, advocacy of science, brave exploration, dare to practice have been formed in colleges and universities through the above innovative engineering education reform.

In this work, a high precision adaptive slope compensation circuit is proposed used in DC-DC converter for System-on-Chip Power Management. Compared with the conventional adaptive slope compensation circuit, this work uses the comparator to sample the output voltage and the input voltage, so that the accuracy has been greatly improved. In this paper, the circuit is designed based on UMC 0.18-μm CMOS Technology and verified by Cadence simulation environment. Simulation results show that, the compensation precision of the slope can reach more than 96% when changes the input voltage with output voltage fixed or changes the output voltage while keeping input voltage constant.

Principle and Application of Microcontroller Unit” is the core course in Circuits and Systems. Microcontroller Unit is widely used in industrial production. Students with basic design ability of MCU system will have good prospects. The teaching of MCU is mainly based on two simulation softwares, Proteus and Keil. They are very helpful in teaching MCU, but the shortcomings are obvious. The simulation can only test the functionality of the circuit and the correctness of the program, and cannot verify the reliability and practicability of the designed system. This paper proposes an experiment-based MCU teaching method, which combines theory with practice to improve students' practical ability and comprehensive ability.

The combination of engineering education and research is an effective method to construct high performance college teachers, which is a cradle to cultivate young teachers. Teaching and research group of "circuit analysis and electronic circuits" in our university promotes experimental engineering education by scientific research through long-term practice and summary in terms of training students, several detailed individual innovative experiments derived from scientific research of teachers are given, a virtuous cycle between engineering education and scientific research can stimulate interest and the motivation of students. Furthermore, engineering education and experimentat teaching promoted by scientific research can get rid of the restraint of the conventional mechanical passive teaching scheme and can refax the dilemma of teaching and learning, finally, the interest and ¡earning motivation of students can effectively be stimulated.

This paper presents a capacitive array optimization technique capable to improve the Spurious Free Dynamic Range (SFDR) and Signal-to-Noise-and-Distortion Ratio (SNDR) of Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) for smart sensor specifications. Monte Carlo simulation results show that the proposed optimization technique makes the SFDR, SNDR and (Signal-to-Noise Ratio) SNR better definitely concentrated, which means with a spread between maximum and minimum value much smaller than the one obtained by conventional calibration techniques. This gives rise to more stable and better performances. The averaged SFDR improves from 72.9 dB to 91.1 dB with σu = 0.4%, the 18.2 dB improvement required an off-line processing and a small digital logic circuits.

Closed‐form expressions of the upper and lower bounds of the outage probability are derived for interference‐limited dual‐hop decode‐and‐forward and channel‐state‐information‐assisted amplify‐and‐forward relay systems using three relay selection (RS) schemes [optimal source–relay link (OSRL) scheme, optimal relay–destination link (ORDL) scheme and optimal source–relay–destination link (OSRDL) scheme] over independent log‐normal fading channels. Multiple interferers at both relay and destination are considered. The diversity order of the targeted cooperative system under the three different RS schemes is analysed. The analysis shows that the asymptotic relative diversity orders (ARDO) for OSRL, ORDL and OSRDL schemes are 2, 2 and ( N + 1) (where N is the number of the relay candidates), respectively. Finally, the ARDO is verified by simulation results.

A parallel dual matrix method that considers all cases of numerical relations between a mixing matrix and a separating matrix is proposed in this letter. Different constrained terms are used to construct cost function for every subalgorithm. These constrained terms reflect numerical relation. Therefore, a number of undesired solutions are excluded, the search region is reduced, and the convergence efficiency of the algorithm is ultimately improved. Moreover, any parallel subalgorithm is proven to converge to a desired separating matrix only if its cost function converges to zero. Computer simulations indicate that the algorithm efficiently performs blind signal separation.

In this paper, analytical models are proposed to study the performance of amplify-and-forward (AF) multi-branch multi-hop (MBMH) wireless relay systems (WRS) over log-normal fading channels. The presented analytical models are used to estimate the end-to-end performance of the MBMH WRS with maximal ratio combining (MRC) and selection combining (SC) schemes. In particular, we derive closed-form expressions for the parameters of the end-to-end signal-to-noise ratio (SNR) of an AF multi-hop chain relay link. Further, we characterize the distribution of the end-to-end SNR and derive closed-form expressions for the mean and standard deviation of the end-to-end SNR's natural logarithm for AF MBMH WRS with MRC scheme, and the probability density function (pdf) for the end-to-end SNR of AF MBMH WRS with SC scheme. Then, under MRC and SC schemes, we analyze the diversity gain by adopting asymptotical relative diversity order (ARDO) and develop accurate analytical expressions for average bit error probability, outage probability, and ergodic capacity, respectively. Our analysis reveals that the computational complexity of the proposed models is acceptably low for practical applications. Numerical and Monte Carlo simulation results are presented to substantiate the accuracy of the proposed analytical models.

A stable and efficient anti-collision protocol is very important for tags identification in many radio frequency identification (RFID) system such as flow productions and automatic controls. In this paper, we introduce an efficient anti-collision protocol named collision tree protocol (CT) and analyze the stability of it in detail. Both theoretical results and experimental results indicate that the performance of CT is only dependent on the number of tags to be identified and not influenced by the distribution of tag IDs and other factors, and the average performance of CT for one-tag identification converges to a constant. According to the definition of the stability of an anti-collision protocol, CT is a stable anti-collision protocol for RFID tag identification. The stability proposed in this paper provides a new performance metric for evaluating the performance of different anti-collision protocols for RFID tag identification. As a stable protocol, the time delay and the power consumption for one-tag identification of CT tend to be constant. Therefore, CT can be applied to various tags identification systems and especially suited to the RFID systems in which both the time delay and the power consumption for tags (or objects) identification are required to be limited and stable.

In this letter, we propose an analytical model to study the performance of cooperative links for time hopping ultra wideband (UWB) systems under two relay models: amplify-and-forward (AF) and decode-and-forward (DF). The effects of multi-user interference (MUI) are considered when deriving closed-form expressions for outage probability and average bit error probability (BEP) over single-path model. Simulation results show that the presented analytical model can accurately predict the link performance.