EDBT 2026 Demo / reviewers in the wild / expert
Andrew Sweeney
dblp:78/889
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 2012
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Applied, interdisciplinary, general and emerging computing · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 67% Embedded and real-time systems · 33% | |
| Software engineering, system software, and programming languages
1 paper |
Requirements engineering and software design · 50% Operating systems · 50% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems
memory management |
0.1 | 1 | 2012 | Increasing Memory Utilization with Transient Memory Scheduling · RTSS 2012 |
Memory systems › memory controller
memory scheduling |
0.1 | 1 | 2012 | Increasing Memory Utilization with Transient Memory Scheduling · RTSS 2012 |
Embedded and real-time systems
real-time scheduling |
0.1 | 1 | 2012 | Increasing Memory Utilization with Transient Memory Scheduling · RTSS 2012 |
Requirements engineering and software design › software architecture › component-based software engineering
component-based systems |
0.0 | 1 | 2012 | Increasing Memory Utilization with Transient Memory Scheduling · RTSS 2012 |
Operating systems › system security › operating system security › protection mechanism › isolation
memory isolation |
0.0 | 1 | 2012 | Increasing Memory Utilization with Transient Memory Scheduling · RTSS 2012 |
Methods — techniques the papers use, named apart from their topics
temporal multiplexing · 0.3
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2012 | Increasing Memory Utilization with Transient Memory SchedulingabstractIn addition to predictability, both reliability and security are increasingly important for embedded systems. To limit the scope of errant behavior in open and mixed criticality systems, a common approach is to raise isolation barriers between software components. However, this decentralizes memory management across all system components. Memory is often cached and quickly accessible in each application. This paper introduces the TMEM system for increasing memory utilization while optimizing for application end-to-end constraints such as meeting deadlines. In addition to the traditional spatial multiplexing of memory, TMEM introduces the predictable temporal multiplexing of memory within caches in a system component, and memory scheduling to continually reallocate memory between components to best benefit the system. We find that TMEM is able to maintain the efficiency of caches, while also lowering both task tardiness and system memory requirements. Jiguo Song, Gabriel Parmer, Andrew Sweeney, Guru Venkataramani |
RTSS | 4 |