Summary In the Top500 and Graph500 lists of the last years, some of the most powerful systems implement a torus topology to interconnect the millions of computing nodes they include. Some of these torus networks are of five or six dimensions, which implies an additional difficulty as the node degree increases. In previous works, we proposed and evaluated the nD Twin (nDT) torus topology to virtually increase the dimensions a torus is able to implement. We showed that this new topology reduces the distances between nodes, increasing, therefore, global network performance. In this work, we present how to build a 5DT torus network using a specific commercial 6‐port network card (EXTOLL card) to interconnect those nodes. We show, using the same number of cards, that the performance of the 5DT torus network we are able to implement using our proposal is higher than the performance of the 3D torus network for the same number of compute nodes.

Summary An nDT torus is a topology where each node comprises 2 identical (n+1)‐port communication cards interconnected by 1 port. By using the current switches or communication cards, this node architecture allows to build torus networks having a greater number of dimensions than networks including only 1 card per node. There are multiple ways to use the ports of the 2 cards to connect a node to other nodes on the nDT torus, and therefore, checking all the configurations is only an affordable problem for small values of n. In this paper, we use artificial intelligence and data mining techniques to obtain the optimal port configuration of all the nodes in the network. We include a performance evaluation that shows nDT torus effectively increases the performance compared with the equivalent torus in resources, with synthetic and application trace–based workloads. We also apply these techniques to 3DT and 5DT tori to confirm the increase in the number of dimensions that does not affect to performance of the nDT torus.

Torus topology is one of the most common topologies used in the current largest supercomputers due to its properties related to cost, implementation or scalability. N-dimensional twin torus (nDT) topology has been proposed to increase the number of dimensions of the torus networks when port-limited low cost expansion cards are available. These topologies have been characterized and evaluated considering only deterministic routing. Adaptive routing algorithms improve communication performance exploiting the path diversity of the torus networks. Due to the particular properties of the nDT torus, designing an adaptive routing algorithm presents a challenge. The peculiarities of the internal link, which interconnects the two communication cards of an nDT torus node, complicate the design of the adaptive routing. In this paper, we study these peculiarities and propose an adaptive routing for nDT tori. Moreover, we show that, by using cards with the same number of ports, we can improve the network performance by building an adaptive nDT torus instead of an adaptive nD torus.

Simulation is often used to evaluate the behaviour and measure the performance of computing systems. Specifically, in high-performance interconnection networks, the simulation has been extensively considered to verify the behaviour of the network itself and to evaluate its performance. In this context, network simulation must be fed with network traffic, also referred to as network workload, whose nature has been traditionally synthetic. These workloads can be used for the purpose of driving studies on network performance, but often such workloads are not accurate enough if a realistic evaluation is pursued. For this reason, other non-synthetic workloads have gained popularity over last decades since they are best to capture the realistic behaviour of existing applications. In this paper, we present the VEF traces framework, a self-related trace model, and all their associated tools. The main novelty of this framework is that, unlike existing ones, it does not provide a network simulation framework, but only offers an MPI task simulation framework, which allows one to use the MPI-based network traffic by any third-party network simulator, since this framework does not depend on any specific simulation platform.

MOTIVATION: Elementary flux modes (EFMs) analysis constitutes a fundamental tool in systems biology. However, the efficient calculation of EFMs in genome-scale metabolic networks (GSMNs) is still a challenge. We present a novel algorithm that uses a linear programming-based tree search and efficiently enumerates a subset of EFMs in GSMNs. RESULTS: Our approach is compared with the EFMEvolver approach, demonstrating a significant improvement in computation time. We also validate the usefulness of our new approach by studying the acetate overflow metabolism in the Escherichia coli bacteria. To do so, we computed 1 million EFMs for each energetic amino acid and then analysed the relevance of each energetic amino acid based on gene/protein expression data and the obtained EFMs. We found good agreement between previous experiments and the conclusions reached using EFMs. Finally, we also analysed the performance of our approach when applied to large GSMNs. AVAILABILITY AND IMPLEMENTATION: The stand-alone software TreeEFM is implemented in C++ and interacts with the open-source linear solver COIN-OR Linear program Solver (CLP).

Torus topology is one of the preferred topologies for the interconnection network in high-performance clusters and supercomputers. Cost and scalability are some of the properties that make torus suitable for systems with a large number of nodes. The 3D torus is the version more extended due to its excellent nearest neighbor. However, some of the last supercomputers have been built using a torus network with five or six dimensions. To obtain an nD torus, 2n ports per node are needed, which can be offered by a single or several cards per node. In the second case, there are multiple ways of assigning the dimension and direction of the card ports. In previous work we defined and characterized the 3D Twin (3DT) torus which uses two four-port cards per node. In this paper we extend that previous work to define the n-dimensional Twin (nDT) torus topology. In this case, we formally obtain the optimal port configuration when (n + 1)-port cards are used instead of 2n-port cards. Moreover, we explain how deadlock problem can appear and propose a simple solution. Finally, we include evaluation results which show performance increases when an nDT torus is used instead of an nD torus with fewer dimensions and with the same computational resources.

Torus topology is one of the most common topologies used in the current largest supercomputers. Although 3D torus is widely used, recently some supercomputers in the Top500 list have been built using networks with topologies of five or six dimensions. To obtain an nD torus, 2n ports per node are needed. These ports can be offered by a single or several cards per node. In the second case, there are multiple ways of assigning the dimension and direction of the card ports. In a previous work we proposed the 3D Twin (3DT) torus which uses two 4-port cards per node, and obtained the optimal port configuration. This paper extends and generalizes that work in order to obtain the optimal port configuration when n dimensions are considered. Thus, the nDT torus topology is presented and defined, and a detailed formal analysis leads to the optimal port configuration. Finally, performance results are included.

Torus is a subclass of direct topologies that was defined in theory to support${\mbi {n}}$dimensions. Although recently some supercomputers have been built on a network with five and six dimensions, the most common case is when only three dimensions are implemented. In the market, there are low-profile communication expansion cards that have a reduced number of ports which is not enough to build tori of a certain number of dimensions. In this paper, we will deal with four-port expansion cards. By means of one of these cards per node, a 2-D torus topology could be built, but not a 3-D torus topology. However, two of these cards could be used to build each node of a 3-D torus topology. In this case, two ports are used to interconnect both cards each other, and the other six ports to connect to six neighbor nodes in the 3-D torus. Theoretically, there are several ways of assigning the dimension and direction of the ports. This paper presents a detailed study of the possible port configurations, and under specific network conditions, the best of them is obtained.

High-radix switches are an attractive option to improve network performance and to reduce network cost, especially in large switch-based interconnection networks. However, there are some problems related to the integration scale to design such single-chip switches. In this paper we describe an interesting alternative for building high-radix switches which basically consists in combining several current smaller single-chip switches to obtain switches having greater number of ports. This approach is independent of the evolution of single-chip switches and will remain valid as integration scale keeps evolving. We discuss about key design issues of this kind of switches and focus on their internal structure. In order to show the relevance of this issue, we obtain the optimal internal configuration of switches for several networks and evaluate the network performance considering different conditions. Simulation results show that with a correct internal switch design, a network based on these high-radix switches achieves similar performance to a network based on single-chip switches, which have the same number of ports as high-radix switches, and which would be unfeasible with the current integration scale.

In large switch-based interconnection networks, increasing the switch radix results in a decrease in the total number of network components, and consequently the overall cost of the network can be significantly reduced. Moreover, high-radix switches are an attractive option to improve the network performance in terms of latency, since hop count is also reduced. However, there are some problems related to the integration scale to design such single-chip switches. In this paper we discuss key issues and evaluate an interesting alternative for building high-radix switches going beyond the integration scale bounds. The idea basically consists in combining several current smaller single-chip switches to obtain switches having greater number of ports. This approach is independent of the evolution of single-chip switches and remains valid as integration scale keeps evolving. Simulation results show that with a correct internal switch design, this alternative achieves almost the same performance as single-chip switches with the same number of ports, which would be unfeasible with the current integration scale.

In large switch-based interconnection networks, increasing the switch radix results in a decrease in the total number of network components. In this paper we evaluate an interesting strategy for building high-radix switches going beyond the integration scale bounds. This approach is independent of the evolution of single-chip switches and will remain valid as integration scale keeps evolving. Simulation results show that with a correct internal switch design, this kind of switches achieves almost the same performance as single-chip switches with the same radix, which would be unfeasible with current integration scale.