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Zahir A. Syed

dblp:79/10967 · DBLP profile ↗
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3ranked-venue papers
1as first author
0since 2021 · last 1983
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Electronic design automation · 79% Performance modeling and evaluation · 21%

Topics — the 8 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
physical design
0.031983
A new statistical model for gate array routing · DAC 1983
On routing for custom integrated circuits · DAC 1982
Incremental processing applied to Steinberg's placement procedure · DAC 1979
Electronic design automation › physical design
routing
0.021983
A new statistical model for gate array routing · DAC 1983
On routing for custom integrated circuits · DAC 1982
Electronic design automation › physical design › routing › VLSI routing
gate array routing
0.011983
A new statistical model for gate array routing · DAC 1983
Performance modeling and evaluation
simulation
0.011983
A new statistical model for gate array routing · DAC 1983
Performance modeling and evaluation › statistical analysis
statistical modeling
0.011983
A new statistical model for gate array routing · DAC 1983
Electronic design automation › physical design › routing
channel routing
0.011982
On routing for custom integrated circuits · DAC 1982
Electronic design automation › physical design › placement
detailed placement
0.011979
Incremental processing applied to Steinberg's placement procedure · DAC 1979
Electronic design automation › physical design
placement
0.011979
Incremental processing applied to Steinberg's placement procedure · DAC 1979

Methods — techniques the papers use, named apart from their topics

statistical model · 0.0channel graph · 0.0steinberg's placement procedure · 0.0
YearPublicationVenuePosition
1983 A new statistical model for gate array routing
Abbas El Gamal, Zahir A. Syed
DAC2
1982 On routing for custom integrated circuits
abstract
This paper presents a novel and effective strategy for routing custom integrated circuits as well as solutions to subproblems associated with this strategy. Given an initial placement of rectangular blocks, the routing strategy includes the following major steps: construction of a channel graph, estimation of channel widths (based on a statistical model for signal nets and topological routing of power and ground nets), placement modification to include the estimated channel widths, topological routing for signal nets, and finally track assignment.
Zahir A. Syed, Abbas El Gamal, Melvin A. Breuer
DAC1
1979 Incremental processing applied to Steinberg's placement procedure
Harold W. Carter, Melvin A. Breuer, Zahir A. Syed
DAC3