Double patterning lithography (DPL) is one of the most promising solutions for the 28nm technology node and beyond. The main idea of DPL is to decompose the layout into two sub-patterns and manufacture the layout by two masks. In addition to traditional analog design constraints, the pre-coloring constraint should also be considered, in which patterns of critical or sensitive modules have predefined masks before layout decomposition to reduce mismatches. In this paper, we present the first work that considers DPL during analog placement and simultaneously minimizes area, wirelength, and DPL conflicts. We first propose an extended conflict graph (ECG) to represent the relation between patterns of analog modules and apply an integer linear programming (ILP) formulation to determine the orientation of each module and the color of each pattern for conflict minimization. ILP reduction schemes are proposed to further reduce the runtime. Finally, we present a three-stage flow and DPL-aware perturbations to obtain desired solutions. Experimental results show that the proposed flow can effectively and efficiently reduce area, wirelength, and DPL conflicts.

The routing quality on RDLs in 3D ICs is affected by the micro-bump location seriously. In this paper, we propose a micro-bump assignment method using order relation to minimize the crossing problem and reduce the detours in RDLs. Experimental results show that our approach can obtain an assignment result with 100% routability and minimal wirelength in global routing.