We introduce a methodology for automated test compression during electrical stress testing of analog and mixed signal circuits. This methodology optimally extracts only portions of a functional test that electrically stress the nets and devices of an analog circuit. We model test compression as a problem of optimizing functional of the transient response. We present a random tree based approach to find optimal solutions for these computationally hard integrals. We demonstrate with an op-amp, VCO and CMOS inverter that the method consistently reduces the length of each test by an average of 93%.

We present Duplex random tree search, an algorithm to optimize performance metrics of analog and mixed signal circuits. Duplex determines the optimal design, the Pareto set and the sensitivity of circuit's performance metrics to its parameters. We demonstrate that Duplex is 5× faster than the state-of-the-art and finds the global optimum for a design whose previously published result was a local optimum. We show our algorithm's scalability by optimizing a system-level post-layout charged-pump PLL circuit.

We present an automated directed random input stimulus generation algorithm with high coverage for nonlinear analog circuits. Our methodology is able to generate input stimuli to meet two kinds of objectives: 1) to reach user-defined goal regions and 2) increased coverage of state space. The principal benefit of our approach is that it can provide directed input stimulus generation, as opposed to the randomly generated input stimulus by Monte Carlo-based methods. The methodology introduces multiobjective rapidly-exploring random trees (MORRTs), which add a bias and a feedback loop to the standard rapidly-exploring random trees algorithm. The biasing is provided by a statistical inference algorithm. Simultaneous biasing toward goal regions and coverage is possible in MORRT to a user-defined extent. Our methodology generates several input stimuli that are concentrated in the goals or relevant operating regions, while providing high coverage of the state space. We demonstrate the efficiency and scalability of our approach on high-dimensional analog case studies.

Statistical model checking (SMC) is a simulation-based approach for verifying the statistical properties of large, complex systems. If a large number of low-probability events (rare events) is required to be simulated, SMC is extremely time-consuming. In this paper, we present a methodology to accelerate the SMC of hardware circuits by generating rare events with a higher frequency. Unlike existing techniques, our methodology can be applied to circuits with multiple rare-event regions. We first sample the circuit uniformly to quickly generate a set of rare events. We employ variational Bayes, a variational inference technique used in machine learning, to infer the distribution of the rare events in the circuit. We then bias the statistical distribution toward these rare event regions. Finally, we employ the SMC using the biased distribution and adjust for the bias that we introduce. The use of variational Bayes enables our methodology to distinguish between multiple rare event regions in the circuit. We demonstrate the effectiveness of our biasing approach on two real-world hardware circuits. We consider the analog (i.e., continuous-time) behavior of these circuits. For an SRAM memory cell, which has a single failure region, we show that our approach provides around 31× speedup over regular SMC while verifying whether the failure rate is less than 10-4. For a successive approximation ADC circuit, which has multiple failure regions, we demonstrate a speedup of 42× while verifying whether the failure rate is less than 10-5.

Because of complexity of analog circuits, their verification presents many challenges. We propose a runtime verification algorithm to verify design properties of nonlinear analog circuits. Our algorithm is based on performing exploratory simulations in the state-time space using the Time-augmented Rapidly Exploring Random Tree (TRRT) algorithm. The proposed runtime verification methodology consists of i) incremental construction of the TRRT to explore the state-time space and ii) use of an incremental online monitoring algorithm to check whether or not the incremented TRRT satisfies or violates specification properties at each iteration. In comparison to the Monte Carlo simulations, for providing the same state-space coverage, we utilize a logarithmic order of memory and time.

We propose a methodology for reachability analysis of nonlinear analog circuits to verify safety properties. Our iterative reachable set reduction algorithm initially considers the entire state space as reachable. Our algorithm iteratively determines which regions in the state space are unreachable and removes those unreachable regions from the over approximated reachable set. We use the State Partitioning Tree (SPT) algorithm to recursively partition the reachable set into convex polytopes. We determine the reachability of adjacent neighbor polytopes by analyzing the direction of state space trajectories at the common faces between two adjacent polytopes. We model the direction of the trajectories as a reachability decision function that we solve using a sound root counting method. We are faithful to the nonlinearities of the system. We demonstrate the memory efficiency of our algorithm through computation of the reachable set of Van der Pol oscillation circuit.

We present a methodology to generate goal-oriented test cases for verifying nonlinear analog circuits. We use a learning-based approach to identify the goal regions in circuit's state space. We use the information that we learn to guide the growth of Rapidly-exploring Random Trees (RRTs) towards these goal regions. Compared to previous approaches for test generation, our methodology generates several test cases of the circuit that are more concentrated in the relevant operating regions. We demonstrate the effectiveness of our approach on typical case studies. We show that our methodology can be used to generate test cases for undesirable behavior that was previously hard to detect.