The objective of the present paper is to investigate possible methods to reduce a program's execution time by detecting and converting automatically the more frequently executed program parts, mostly inner loops, into microcode.

The objective of the present study has been to investigate possible methods to reduce a program's execution time by detecting and converting automatically the more frequently executed program parts, mostly inner loops, into microcode. The methods proposed were static loading of inner loops, selective loading of inner loops, over-lay of inner loops, and user-aided scheme. Using Fortran programs as the test programs, a simulation program was written to measure the gain achieved by each method. A final gain between 1.587 and 4.76 was achieved by the proposed methods for memory speed ratios between 3 and 8. It was found that 90% of the final gain of the test programs could be obtained with writable control memory requirements that were less than 40% of the final requirement.

A method of realizing arbitrary combinational switching functions with multiplexers is derived. These circuits are divided in two classes where the first allows only uncomplemented variables as control inputs and the second has unrestricted inputs. The selected inputs to each multiplexer in the first class of circuits (tree circuits) are shown to be residue functions of the output function. Using this fact, it is demonstrated that many functional properties simplify realization procedures.

This paper investigates some of the problems that arise when several microprocessors share a common control memory and a common main memory. The performance with respect to both control and main memory accessing conflicts is measured for several system configurations by means of a simulation program. The program tests a set of Digital Scientific Meta 4's operating in IBM 1130 emulation mode.

A sequential network is said to be controllable if there exists at least one integer k such that it is possible to transition between any pair of arbitrary states ( S α , S β ) in exactly k steps. In this paper, necessary and sufficient conditions are given for a nonlinear sequential network to be controllable. Strong connectedness is a necessary condition for controllability. It is shown that the existence of two cycles C 1 and C 2 on a strongly connected sequential network, whose cycle lengths L 1 and L 2 are relatively prime, is both necessary and sufficient for controllability. Simple test procedures are also developed which determine if a sequential network is controllable and which determine the transition sequences.

Two vector operators θ and γ are introduced. The next-state operator θ allows one to calculate the successors of a set of states {G} from a binary nonlinear feedback shift register. The past-state operator γ allows one to calculate the predecessors of a set of states {G}. Both of these operators, which can be easily programmed on a digital computer, can be used to analyze autonomous and nonautonomous feedback shift registers. Analysis procedures using these operators are given for determining the cycle set of an arbitrary nonlinear FSR, for deciding if the state diagrams of the FSR are connected or strongly connected, and also for determining if the FSR is controllable.

It is shown in this paper that the stable feedback shift registers, when classified according to Hamming weight (the number of fundamental product terms in expanded sum of products form), are binomially distributed, i.e., are (2 n - n - 1 w ) stable feedback shift registers of order n with Hamming weight equal to w . Using this relationship, a recursive algorithm is established which will generate all stable feedback shift registers of order n . Formulas are also given for determining the number of stable feedback shift registers which have j + 1 starting states and j + 1 branch states, 0 ≤ j ≤ 2 n -1 - 1.

In this paper a relationship among distinct Pn+1cycles, distinct stable maximum transient feedback shift registers of order n+1, and stable feedback shift registers of order n will be presented. In the course of the discussion, two algorithms will be introduced. The first will provide a one-to-one mapping between distinct stable feedback shift registers of order n and distinct stable maximum-transient feedback shift registers of order n+1. The second will provide a one-to-one mapping between distinct maximum transient feedback shift registers of order n+1 and distinct Pn+1cycles. As a corollary to these relationships, an enumeration of the stable feedback shift registers is obtained.