Ethernet Passive Optical Network (EPON) systems have been deployed widely as a broadband access network solution. Recently, 10Gigabit EPON (10G-EPON) has been investigated as one of the next optical access network solutions. In 10G-EPON system, one of the key technologies is the Dynamic Bandwidth Allocation (DBA) which achieves the high bandwidth efficiency and provides high data throughput for the end users. In this paper, we propose a new DBA algorithm: Adaptive DBA (AD-DBA) which is adaptively switching status-reporting method and traffic monitoring method according to the traffic load and achieves high data throughput and low data transmission delay. Then, we report the evaluation results of proposed algorithm with our 10G-EPON prototype system.

The shared-buffering architecture is promising to make a large-scale ATM switch with small buffer size. However, there are two important problems, namely, memory-access speed and complex-control implementation. Advanced 0.5 /spl mu/m CMOS technology now makes it possible to integrate a huge amount of memory, and enables us to apply more sophisticated architecture than ever before. We propose the funnel-structured expandable architecture with shared multibuffering and the advanced searchable-address queueing scheme for these two problems. The funnel structure gives a flexible capability to build various sizes of ATM switches which are proportional to the number of LSI chips. The searchable-address queue, in which all the addresses of the stored cells for different output ports are queued in a single-FIFO hardware and the earliest address is found by the search function provided inside the queue, can reduce the total memory capacity drastically, and enables the address queue to be contained inside the LSI chip. This technique also has a great advantage for implementing the multicast and multilevel priority-control functions. A 622 Mbit/s 32/spl times/8 ATM switch LSI chip set, which consists of a BX-LSI and a CX-LSI, is developed using 0.5 /spl mu/m pure CMOS technology. By using four chip sets, a 622 Mbit/s 32/spl times/32 switch can be installed on one board.

The design and implementation of the transport layer of a native ATM (asynchronous tranfer mode) protocol stack and its embedding into an overall architecture that provides end-to-end quality of service (QOS) is presented. Within this architecture, the typical transport functionalities are enlarged with QOS monitoring and adaptation mechanisms. A QOS-based API (application programming interface) is proposed that shields application programmers from the complexity of QOS management and control. Both unicast and multicast connections supporting interactive multimedia applications are considered.

There are several schemes to provide multicast function in an ATM switch. The authors have proposed a new multicast scheme in a shared buffering ATM switch. They discuss the cell-loss performance of ATM switch to compare various schemes. Computer simulation shows that this scheme achieves the best cell-loss performance and has a great advantage in the buffer size. Implementation of an LSI chip set and a 622 Mb/s 8/spl times/8 ATM switch board is also explained.>