Under process, voltage, and temperature variations, SRAM cell stability largely fluctuates from the nominal value. In the design step, SRAM cell optimization while ignoring the fluctuation induces the yield loss for the stability. Variation-aware optimization of an SRAM cell can prevent the yield loss problem by considering the mean and variance of SRAM cell stability when finding optimal design parameters. This paper proposes a novel SRAM optimization method that uses a deep neural network (DNN). Multiple DNNs from ensemble techniques represent the mean and variance of SRAM cell stability for the nominal design parameters. Subsequent sensitivity analysis of DNN extracts the K design parameters that have the most dominant effects on the mean and variance of SRAM cell stability. Then multidimensional optimization is used to find the optimal values of these K parameters to maximize the mean stability while minimizing its variance. The proposed method achieved an average of 2% error compared to MC simulation. The proposed optimization method takes only 561 s to provide the most optimal design parameter values of an SRAM cell.

This paper presents a power management policy that exploits reinforcement learning to increase power efficiency of mobile device systems. Our Q-learning-based policy predicts a system’s characteristics and learns power management controls to adapt to the system’s variations. Therefore, we can flexibly manage the system power regardless of the application scenario and can achieve lower energy per QoS compared to previous dynamic voltage/frequency scaling governors. To minimize the process overhead, we implemented our power management policy as hardware; the hardware-implemented policy reduced the average latency up to 40× compared to the software-implemented policy.

Variation-aware leakage analysis becomes an essential design process as the technology node continuously shrinks. This article proposes a novel additive statistical leakage analysis method that uses exponential mixture model (EMM) to estimate the leakage distribution. Using a few leakage data for sub-blocks of an input circuit, we estimate any shape of leakage distribution regardless of new process nodes or operating conditions. Leakage distribution of an input circuit can be obtained by adding the leakage distributions of the sub-blocks. The proposed addition step sequentially adds the leakage distributions of sub-blocks that are expressed as EMMs. Before the addition step, we improve the accuracy by handling linear dependence among leakage simulation data of sub-blocks. In addition, we propose a method to reduce the number of components of an EMM to prevent exponential increase in runtime and memory during the addition process. The proposed method achieved 43.6 times improvement in goodness-of-fit of the estimated cumulative density functions compared to the best results of other analytic model-based methods.

This paper proposes a statistical approach to modeling the single-sided read static noise margin (RSNM) of a 6-transistor SRAM cell. The proposed modeling considers threshold voltage (Vth), channel length, and width variations. In addition, it considers Vth roll-off and drain-induced barrier-lowering effect of short channel transistors. The proposed method needs only a few samples to calculate the coefficients of the proposed equation. Using the calculated analytic equation, the proposed method can offer feedbacks for design improvements. In goodness-of-fit tests, the proposed method achieved about 89% and 99% improvements in the K-S statistic and the chi-square statistic compared with the Quasi-Monte Carlo method for the same number of samples. Also, compared with the previous method based on an analytic model, the proposed method achieved about 91% and 98% improvements in the goodness-of-fit tests.

This paper presents a logic resynthesizing of FPGA from a downloaded bitstream data for Xilinx 7 series FPGA. This study focuses on the LUT logic reconstructing, which is a primitive logic unit in FPGA. The approach generates all possible logic for a LUT trying to various examples. The generated files are compared with each other that are used to construct the truth table of the LUT. The proposed algorithm extracts the logic configuration by analyzing the bitstream and comparing it with the constructed truth table. The resynthesized circuits provide the input and output pin information assigned in the LUT. The algorithm can be expanded to the previous version of Xilinx 7 series. This study will be helpful for security enhancing of FPGA and development of logic synthesis technique.

This paper presents a new static caption detection method that uses the census transform (CT) and motion vector (MV) for frame rate up-conversion. The proposed method splits a frame into several blocks and detects the static regions using CT and MV. CT is used to consider the spatio-temporal consistency of the texture and MV is used to remove the non-static regions containing moving objects. Next, it corrects the falsely detected regions by performing the outlier removal and inward filling. Finally, it detects the static caption based on the existence of global motion. In the experimental results, the average F1 score of the proposed method was up to 0.704 higher than those of the benchmark methods.

This paper proposes novel noniterative mean-shift-based image segmentation that uses global and local attributes. The existing mean-shift-based methods use a fixed range bandwidth, and hence their accuracy is dependent on the range spectrum of an image. To resolve this dependency, this paper proposes to modify the range kernel in the mean-shift process to be anisotropic. The modification is conducted using a global attribute defined as the range covariance matrix of the image. Further, to alleviate oversegmentation, the proposed method merges the segments having similar local attributes more aggressively than other segments. The local attribute for each segment is defined as the sum of the variances of the chromatic components. Finally, to expedite the processing, the proposed method uses a region adjacency graph (RAG) for the merging process, thus differing from the existing linked mean-shift-based methods. In the experiments on the Berkeley segmentation data set, the use of the global and local attributes improved segmentation accuracy; the proposed method outperformed the state-of-the-art linked mean-shift-based method by showing an improvement of 2.15%, 3.16%, 3.32%, and 1.90% in probability rand index, segmentation covering, variation of information, and F-measure, respectively. Further, compared with the benchmark method, which uses the dilating and merging scheme, the proposed method improved the speed of the merging process 42 times by applying the RAG.

This paper proposes a foreground-based approach to generating a depth map which will be used for 2D-to-3D conversion. For a given input image, the proposed approach determines if the image is an object-view (OV) scene or a non-object-view (NOV) scene, depending on the existence of foreground objects which are clearly distinguishable from the background. If the input image is an OV scene, the proposed approach extracts a foreground using block-wise background modeling and performs segmentation using adaptive background region selection and color modeling. Then, it performs segment-wise depth merging and cross bilateral filtering (CBF) to generate a final depth map. On the other hand, for the NOV scene, the proposed approach uses a conventional color-based depth map generation method [9] which has simple operations but provides a 3D depth map of good quality. Human beings are usually more sensitive to depth map quality, and 3D images, for OV scenes than for NOV scenes. With the proposed approach, it is possible to improve the quality of a depth map for OV scenes than using the conventional methods only. The performance of the proposed approach was evaluated through the subjective evaluation after 2D-to-3D conversion using a 3D display, and the proposed one provided the best depth quality and visual comfort among the benchmark methods.

This brief presents an efficient approach to statistical static timing analysis (STA), which estimates the system delay of statistical STA through deterministic STA. In statistical STA, the system delay is modeled as a function of random variables, so it is commonly expressed as a probability density function (pdf). Therefore, to estimate the system delay of statistical STA through deterministic STA, we must find the relationship between an arbitrary percentile point on the pdf of the system delay and the gate delays used in deterministic STA. However, there is no closed-form equation for an arbitrary percentile point on the pdf of the system delay, we derive an analytic expression for the upper bound of an arbitrary percentile point on the pdf of the system delay. This allows us to obtain the corresponding gate delays that are used to estimate the upper bound of the percentile point on the pdf of the system delay through deterministic STA. Experimental results indicate that the percentile point on the pdf of the system delay obtained with statistical STA is strictly bounded by the upper bound of the percentile point obtained with the proposed method within an average 6% difference range.

This study presents an advanced histogram‐based image segmentation method that enhances image segmentation quality, while greatly reducing the computational complexity. Unlike existing histogram‐based methods, the authors optimise the size of bins in the colour histogram by using human perception‐based colour quantisation and the clustering centroids are selected effectively without using a complex process. Additionally, an over‐segmentation removal technique based on connected‐component labelling is employed. This improves the segmentation quality by connectivity analysis. A comparison between the experimental results on the Berkeley Segmentation Dataset by the proposed method and the benchmark methods demonstrated that the proposed method enhanced the segmentation quality by improving the Probabilistic Rand Index and the Segmentation Covering values compared with those of the benchmark methods. The computation time using the proposed method is reduced by up to 91.63% compared with the computation time using benchmark methods.

Health monitoring system is one of most important and practical applications of wireless sensor network (WSN). Even though various health monitoring devices based on WSN are used, they are still quite limited in the sense of mobility and accuracy. In this paper a new wearable health monitoring system is proposed, which consists of bio-shirt and vital sensor node. Here the accuracy of the measurement of electrocardiogram signal is enhanced, and the sensor node is optimized for the use in WSN. Also, a multi-hop routing protocol is employed to effectively deal with rapid changes in the link between a fast moving target node and static relay nodes. The experiments for various types of movements of an individual wearing the proposed bio-shirt reveal that the proposed system significantly improves the performance of health monitoring based on WSN compared to the existing device.

This paper focuses on statistical optimization and, more specifically, timing yield (TY)-constrained optimization. For cell replacement in timing-constrained optimization, we need an indicator that examines whether or not a timing violation occurs and gives the available timing for a gate. In deterministic optimization, the timing slack is used for this indicator. Although there is an analogous concept of TY slack in statistical optimization, it has not been well utilized. This paper proposes an effective way to use the TY slack for successful statistical optimization. To achieve this, we present an efficient method to calculate the TY slacks of gates and a strategy that uses timing resources for effective statistical optimization. Based on this work, we propose a novel statistical leakage minimization method that uses the TY slack for a gate change metric. The use of TY-based metrics that are appropriate for statistical design ensures that our method has a better optimization performance at a higher speed. Experimental results on ISCAS-85 benchmark circuits show that the leakage minimization method reduces leakage by 25.2% compared to the statistical benchmark method. In addition, our method has a better runtime when the number of gates is high.

Along with the increasing applications of light emitting diodes (LEDs), the need for flexible LED controllers is also increasing. A general purpose processor provides excellent flexibility. However, compared to hard-wired controllers, it provides relatively low performance and its exact operation execution time is hard to predict. In addition, they are more expensive than other types of controllers. This paper presents a 16-bit processor-based LED controller, which consists of an application specific instruction set processor and several peripheral modules. Using a software program, the proposed LED controller provides the flexibility to implement various control schemes with small hardware revision. As using real-time operations only, the programmer can predict the execution time of operations exactly. We implemented the proposed LED controller using a field-programmable gate array (FPGA). The FPGA implementation of the controller runs at 100 MHz, and the system successfully displays motion pictures on the test LED matrix panel of 16×64 RGB pixels.

This paper presents a new approach to enhancing the text readability of the quad RGBW color electrophoretic display (EPD). In the color EPD, text characters are jagged due to its low resolution and the jaggedness degrades the readability of the text. However, text characters are usually black-and-white, and for the black-and-white character, it is possible to improve readability by relocating the character sampling points at the sub-pixel level. Based on this, the proposed approach reduces the characters' jaggedness and enhances the text readability. In implementation, we used two-dimensional contrast sensitivity function and discrete Fourier transform to select the best sampling points. In addition, we applied the proposed method only to text areas after text detection. In the experiments using test images, the proposed method clearly increased the text readability without inducing any visual artifacts in non-text area.

This paper proposes Integer-pel Motion Estimation (IME) specific instructions and their hardware architecture for Application Specific Instruction-set Processor (ASIP). With parallel SAD Processing Elements (PEs) using pattern information, the proposed IME instruction supports not only the full search algorithm but also various fast search algorithms. Moreover, the revisiting prevention technique enables that the proposed ASIP can efficiently perform the fast search operations. The gate count is 43K gates for each Processing Element Group (PEG) which has 256 SAD PEs. The proposed ASIP with eight PEGs runs at 160MHz and can handle 1080p@30 frames in real-time.

This paper proposes a dynamic global backlight dimming algorithm based on the analysis of the cumulative distribution function (CDF) of the image histogram. For each intensity level, the convexity of the CDF is calculated using the distance to the uniform histogram curve. Using these values, the proposed algorithm characterizes the shape of the CDF to find the proper clipping ratio. This ratio enables to get the maximum level data beyond which the intensity levels are clipped, as the results of backlight dimming but image distortion. The experimental results show that the proposed algorithm gives a good compromise between backlight power reduction and image quality preservation, quantified by the PSNR metric.

In this letter, we present a new motion estimation algorithm for frame rate up-conversion. The proposed dual motion estimation algorithm enhances the estimation accuracy of motion vectors by using the unidirectional and bidirectional matching ratios of blocks in the previous and current frames. In addition, the proposed motion estimation approach uses motion vector validity to evaluate the accuracy of motion vectors thereby avoiding false motion vectors. In experiments using benchmark image sequences, the proposed motion estimation algorithm improved the average peak signal-to-noise ratio of interpolated frames by up to 2.272 dB, when compared to conventional motion estimation algorithms. For the comparison of the perceptual image quality using the structural similarity, the average value of the proposed dual motion estimation was by up to 0.062 higher than those of the conventional algorithms.

This paper presents a novel method for full-chip statistical leakage estimation that considers the impact of process variation. The proposed method considers the correlations among leakage currents in a chip and the state dependence of the leakage current of a cell for an accurate analysis. For an efficient addition of the cell leakage currents, we propose the virtual-cell approximation (VCA), which sums cell leakage currents sequentially by approximating their sum as the leakage current of a single virtual cell while preserving the correlations among leakage currents. By the use of the VCA, the proposed method efficiently calculates a full-chip leakage current. Experimental results using ISCAS benchmarks at various process variation levels showed that the proposed method provides an accurate result by demonstrating average leakage mean and standard deviation errors of 3.12% and 2.22%, respectively, when compared with the results of a Monte Carlo (MC) simulation-based leakage estimation. In efficiency, the proposed method also demonstrated to be 5000 times faster than MC simulation-based leakage estimations and 9000 times faster than the Wilkinson's method-based leakage estimation.

Electrical-logic (ELogic) is a form of circuit modeling and simulation that solves for the amount of time required for a network variable to make a particular change, rather than solving for the network variables at the given time point as in conventional circuit simulation. Three ELogic algorithms are presented. The algorithms are based on the nodal analysis method and provide a continuous speed-precision tradeoff between the circuit level and logic/switch level, as well as providing more accurate timing information than existing strength-oriented logic simulation or switch-level simulation at comparable speed. These ELogic algorithms have been used to implement both a simulator, ELOSIM, and a timing verifier, E-Crystal, and experimental results from these programs are also included.>

A new delay modeling technique for accurate timing verification of digital MOS circuits is presented. The technique is based on the ELogic approach and provides the user with a continuous speed-accuracy trade-off in addition to more accurate timing information than available with existing switch-level timing verifiers. The new technique has been implemented in the Crystal timing analyzer and experimental results comparing this method with those used in Crystal are included. Comparisons indicate that the ELogic-based approach, while slower than present approaches, provides a more robust and more accurate delay analysis at the switch level.