We present a novel scan architecture for simultaneously reducing test application time and test power (both average and peak power). Unlike previous works where the scan chain is partitioned only based on the excitation properties of the flip-flops (FFs), our work considers both the excitation and propagation properties of the scan FFs. In the proposed scan architecture, the scan chain is partitioned to maximize the overlapping between the excitation and propagation on different fault sets. The scan architecture also allows the entire set of detectable faults in the circuit under test (CUT) to be detected with only a portion of the scan elements active at a time, and thereby completely eliminates the need for the "serial full-scan" mode which is inefficient for both the test time and test power. Experimental results show that by introducing minimal hardware overhead, and without sacrificing fault coverage, an average peak power reduction of 22.8%, average power reduction of 41.6%, and an average reduction of 18.5% on the test application time can be achieved, compared with the ordinary full-scan architecture

This paper introduces a new cooperative traversal on the partitioned finite-state-machine (FSM) space to generate test stimuli for both sequential test generation and design validation. The new features for this logic-simulation-based automatic test pattern generation (ATPG) include: (1) cooperative search that exploits orthogonality is performed on two global state partition sets; (2) feedback information is dynamically extracted from characteristic states (each characteristic state examines a subset of corner cases of the design) to prune away redundant search spaces; (3) different from dynamic partitioning, interactions between two global partition sets are emphasized in the proposed approach. The proposed cooperative search is similar to a cooperative two-player game, where each partition set presents the state space for a player. Experimental results show that test vectors generated by such a cooperative search can yield both higher coverage and up to 5 times reduction on test generation time

We present a new BIST (built-in-self-test) architecture for system-on-a-chip (SOC), which can test a cluster of embedded sequential cores simultaneously. The compressed spectrum for a cluster of cores under test is computed by performing spectral analysis individually on all cores. Because there is no need to combine the cores to extract the spectrum for the entire cluster, the computation complexity is greatly reduced. For each individual core, we propose an interleaved state relaxation on the compacted test sequence for its characteristic fault set, leading to a partially specified, interleaved sequence which can be merged in a much easier way. A delay network and a switching network are added selectively to allow for more aggressive merging of spectra. Experimental results show that the same level of fault coverage can be achieved for each individual core with negligible hardware overhead, while the test application time for testing the entire cluster can be reduced by up to four times and the test data storage requirement is reduced by up to 42 percent.

We present a new low-power BIST (built-in-self-test) for sequential circuits. State correlation analysis is first performed on the flip-flop values in the relaxed, compacted sequence for the undetected faults to extract spatial correlations among the flip-flops. The extracted spatial correlation matrix not only provides additional metrics through which the scan order may be altered, but also allows us to omit some flip-flops in the scan chain. By leaving flip-flops that need less control out of the scan chain, we can reduce transitions on those flip-flops, thereby reducing the overall power and energy. The omission of flip-flops are done in a way that the fault coverage is unaffected. Furthermore, reordering of the flip-flops in the scan chain allows the generated patterns to be more compatible with the state sequence necessary for exciting the random-pattern-resistant faults. Our experiments show that the same or higher fault coverage can be achieved with less energy (and average power) - average power of 48.5% is reduced, with the maximum reduction of 73%.

We present a new method of built-in-self-test (BIST) for sequential circuits and system-on-a-chip (SOC) using characteristic faults and circuitspecific spectral information in the form of one or more Hadamard coefficients. The Hadamard coefficients are extracted from the test sequences for a small set of characteristic faults of the circuit. By extracting a few characteristic faults from the circuit, we show that detection of these characteristic faults is sufficient in detecting a vast majority of the remaining faults in the circuit. The small number of characteristic faults allows us to reduce the coefficients necessary for BIST. State relaxation is performed on the compacted test sequences to reduce the spectral noise further. Since we are targeting only a very small number of characteristic faults, the execution times for computing the spectra are greatly reduced. Our experimental results show that our new method can achieve high BIST coverage with both lower computational efforts and storage, with very few characteristic faults.