Ring-Learning-with-Errors (RLWE) has emerged as the foundation of many important techniques for improving security and privacy, including homomorphic encryption and post-quantum cryptography. While promising, these techniques have received limited use due to their extreme overheads of running on general-purpose machines. In this paper, we present a novel vector Instruction Set Architecture (ISA) and microarchitecture for accelerating the ring-based computations of RLWE. The ISA, named B512, is developed to meet the needs of ring processing workloads while balancing high-performance and general-purpose programming support. Having an ISA rather than fixed hardware facilitates continued software improvement post-fabrication and the ability to support the evolving workloads. We then propose the ring processing unit (RPU), a high-performance, modular implementation of B512. The RPU has native large word modular arithmetic support, capabilities for very wide parallel processing, and a large capacity highbandwidth scratchpad to meet the needs of ring processing. We address the challenges of programming the RPU using a newly developed SPIRAL backend. A configurable simulator is built to characterize design tradeoffs and quantify performance. The best performing design was implemented in RTL and used to validate simulator performance. In addition to our characterization, we show that a RPU using 20.5mm2of GF12nm can provide a speedup of 1485× over a CPU running a 64k, 128-bit NTT, a core RLWE workload.

StereoBit is an embedded application for the SpaceCube family of hybrid onboard processors developed by NASA's Goddard Space Flight Center under sponsorship of the Earth Science Technology Office. StereoBit applies structure from motion algorithms to measure disparities between clouds being tracked from multiple angles to enable 3D resolution of atmospheric motion, which is an important Decadal Survey objective. Our Advanced Information Systems Technology project has the objectives of developing and demonstrating StereoBit for a future mission architecture employing a constellation of CubeSats and to mature the capabilities of the community to program the SpaceCube- family of processors for science applications.

This paper presents updates to the Virtual Constellation Engine (VCE), a simulator and emulator which enables modeling of sensing, computation, and communication of multi-platform remote sensing systems. Users can launch heterogeneous constellations, describe different on-board processing configurations, and simulate and verify autonomous operations. Updates in the past year include emulation of on-board computing utilizing cloud based processors, inclusion of the Delay Tolerant Networking (DTN) protocol in the communication modeling, and visualization and diagnostic tools which facilitate analysis of the distributed system. To illustrate the benefits, VCE was utilized in the development of on-board processing implementation of a new, high data rate sensor, Multispectral, Imaging, Detection, and Active Reflectance (MiDAR), for both an embedded Nvidia Tegra GPU and a Xilinx MPSoC FPGA achieving a 7.6x speedup over a desktop workstation and enabling this application for integration into a distributed sensing system.

This work presents the Virtual Constellation Engine (VCE), a software framework and run-time system designed to facilitate exploration of different remote sensing constellation and sensor web configurations from an on-board processing perspective, using the cloud. Users can launch heterogeneous constellations, describe different on-board processing configurations, and simulate and verify autonomous operations. VCE eases development for applications leveraging complex compute resources and has been demonstrated on Amazon Web Services to provide speedups over 20,000× of state of practice systems.

Research in logic encryption over the last decade has resulted in various techniques to prevent different security threats such as Trojan insertion, intellectual property leakage, and reverse engineering. However, there is little agreement on a uniform set of metrics and models to efficiently assess the achieved security level and the trade-offs between security and overhead. This paper addresses the above challenges by relying on a general logic encryption model that can encompass all the existing techniques, and a uniform set of metrics that can capture multiple, possibly conflicting, security concerns. We apply our modeling approach to four state-of-the-art encryption techniques, showing that it enables fast and accurate evaluation of design trade-offs, average prediction errors that are at least 2× smaller than previous approaches, and the evaluation of compound encryption methods.

Conventional computing has been dominated by one or more uniform processor cores coupled with Dynamic RAM. However, heterogeneous computing (processor cores coupled with accelerators such as FPGAs) are becoming readily available to a broad market. Also, with the introduction of novel technologies (Hybrid Memory Cube, High Bandwidth Memory, etc.), memory performance characteristics are changing abruptly. This paper proposes Volcan, a framework that abstracts the different memory technologies, leverages high-level synthesis, and partial reconfiguration to increase the portability and productivity of application developers interested in heterogeneous computing. Three platforms were tested with three sample applications. The results indicate that the framework introduces little overhead while exposing the bandwidth advantages of these new memory technologies.

We present Hot & Spicy an open-source infrastructure and tool suite for integrating FPGA accelerators in Python applications, provided entirely as Python source code and available at https://spicy.isi.edu. This suite of tools eases the packaging, integration, and binding of accelerators and their C/C++ based drivers callable from a Python application. The Hot & Spicy tools can: (1) translate Python functions to HLS-suitable C functions, (2) generate Python C wrapper bindings, (3) automate the FPGA EDA tool flow, and (4) retarget Python source code to use accelerated libraries. For FPGA experts, this enables increased productivity and supports research on each stage of the flow by providing a framework to integrate additional compilers and optimizations. For everyone else this enables fast, consistent, acceleration of applications on FPGAs. We describe the design principles and flows for supporting high-level Python abstractions in an FPGA development flow. Then we evaluate the overheads of calling C/C++ routines from Python. Lastly, we show the results of accelerating a kernel in a Python image processing application and achieve a 39,137× speedup over the original Python implementation, and 6× speedup over an high-performance, hand-optimized OpenCV library implementation.

As modern FPGAs evolve to include more heterogeneous processing elements, such as ARM cores, it makes sense to consider these devices as processors first and FPGA accelerators second. As such, the conventional FPGA development environment must also adapt to support more software-like programming functionality. While high-level synthesis tools can help reduce FPGA development time, there still remains a large expertise gap in order to realize highly performing implementations. At a system-level the skill set necessary to integrate multiple custom IP hardware cores, interconnects, memory interfaces, and now heterogeneous processing elements is complex. Rather than drive FPGA development from the hardware up, we consider the impact of leveraging Python to accelerate application development. Python offers highly optimized libraries from an incredibly large developer community, yet is limited to the performance of the hardware system. In this work we evaluate the impact of using PYNQ, a Python development environment for application development on the Xilinx Zynq devices, the performance implications, and bottlenecks associated with it. We compare our results against existing C-based and hand-coded implementations to better understand if Python can be the glue that binds together software and hardware developers.

In this article, we propose a real-time anomaly detection framework for an NoC-based many-core architecture. We assume that processing cores and memories are safe and anomaly is included through a communication medium (i.e., router). The article targets three different attacks, namely, traffic diversion, route looping, and core address spoofing attacks. The attacks are detected by using machine-learning techniques. Comprehensive analysis on machine-learning algorithms suggests that Support Vector Machine (SVM) and K-Nearest Neighbor (K-NN) have better attack detection efficiency. It has been observed that both algorithms have accuracy in the range of 94% to 97%. Additional hardware complexity analysis advocates SVM to be implemented on hardware. To test the framework, we implement a condition-based attack insertion module; attacks are performed intra- and intercluster. The proposed real-time anomaly detection framework is fully placed and routed on Xilinx Virtex-7 FPGA. Postplace and -route implementation results show that SVM has 12% to 2% area overhead and 3% to 1% power overhead for the quad-core and 16-core implementation, respectively. It is also observed that it takes 25% to 18% of the total execution time to detect an anomaly in transferred packets for quad-core and 16-core, respectively. The proposed framework achieves 65% reduction in area overhead and is 3 times faster compared to previous published work.

Information security in FPGAs is at risk; during system operation, data and usage patterns can potentially get imprinted into a chip's physical characteristics, allowing an attacker to later recover intellectual property or cryptographic secrets. Can “data burn-in” vulnerabilities in FPGAs be characterized at low cost? Specifically, can slight shifts in path delays due to burn-in be measured with enough precision? This paper contributes methods for self-characterization of delay changes using novel isolation of key FPGA transistors, improved clock sweeping, and enhanced estimation from launch-andcapture data. Hardware experiments on 2048 Xilinx Kintex-7 paths demonstrate measurement precision of 30-60 femtoseconds, which is more than 10× finer than previous self-characterization results. Further, results show that unintentional burn-in of FPGA LUT contents does indeed occur and can in some cases be detected within a single week, highlighting the need to deploy countermeasures.

This work describes a new non-destructive method to determine the presence of anomalies such as Hardware Trojans in physical VLSI layer of FPGA, especially in configurable logic blocks and switch blocks. The detection that accounts for spatially correlated intra-die process variations can be achieved by isolating a suspected region where its device characteristic is inconsistent from ones in the physically nearest regions. This method does not require a golden chip to compare with a chip under test and can be performed without expensive testing equipment. In this paper, we present anomaly implementations and emulations as well as experimental results and analysis on anomaly detection from data obtained from Xili1nx Virtex-4, Virtex-5 and Virtex-6 FPGA devices.

Motivated by the proposed NASA HyspIRI mission, our work improves existing Radiation Hardening by Software (RHBSW) techniques with FPGA Fabric Checkpoint/Restart (F2CPR) to bring enhanced hardware/software co-designed fault tolerance to commercial FPGA devices. We evaluate our approach on Fast Lossless (FL) image compression prediction for hyperspectral imagery in order to meet real-time performance requirements that cannot be achieved with aging radiation hardened devices. We report results across several metrics including resource utilization, performance, and an analysis of the vulnerability to Single Event Upsets (SEU) through the use of a hardware based fault injector. Results show low performance overhead (4-8%) achieving a speedup of 11.28× with a hardware accelerated implementation.

Historically, space-based processing systems have lagged behind their terrestrial counterparts by several processor generations due, in part, to the cost and complexity of implementing radiation-hardened processor designs. Efforts such as NASA's SpaceCube seek to change this paradigm, using higher performance commercial hardware wherever possible. This has the potential to revolutionize onboard data processing, but it cannot happen unless the soft error reliability can be characterized and deemed sufficient. A variety of fault injection techniques are used to evaluate system reliability, most commonly fault emulation, fault simulation, laser testing, and particle beam testing. Combining multiple techniques is more complex and less common. In this study we characterize a real-world application that leverages a radiation-hardening by software (RHBSW) solution for the SpaceCube platform, using two fault injection strategies: laser testing and fault emulation. We describe several valuable lessons learned, and show how both validation techniques can be combined to greater effect.

This work presents an open-source bitstream generation tool for Torc. Bitstream generation has traditionally been the single part of the FPGA design flow that could not be openly reproduced, but our novel approach enables this without reverse-engineering or violating End-User License Agreement terms. We begin by creating a library of “micro-bitstreams” which constitute a collection of primitives at a granularity of our choosing. These primitives can then be combined to create larger designs, or portions thereof, with simple merging operations. Our effort is motivated by a desire to resume earlier work on embedded bitstream generation and autonomous hardware. This is not feasible with Xilinx bitgen because there is no reasonable way to run an x86 binary with complex library and data dependencies on most embedded systems. Initial support is limited to the Virtex5, but we intend to extend this to other Xilinx architectures. We are able to support nearly all routing resources in the device, as well as the most common logic resources.

Voltage noise not only detracts from reliability and performance, but has been used to attack system security. Most systems are completely unaware of fluctuations occurring on nanosecond time scales. This paper quantifies the threat to FPGA-based systems and presents a solution approach. Novel measurements of transients on 28nm FPGAs show that extreme activity in the fabric can cause enormous undershoot and overshoot, more than 10× larger than what is allowed by the specification. An existing voltage sensor is evaluated and shown to be insufficient. Lastly, a sensor design using reconfigurable logic is presented; its time-to-digital converter enables sample rates 500× faster than the 28nm Xilinx ADC. This enables quick characterization of transients that would normally go undetected, thereby providing potentially useful data for system optimization and helping to defend against supply voltage attacks.

Traditional approaches to evaluating a system's vulnerability to Single Event Upsets (SEUs) require elaborate and costly radiation beam testing or time-consuming simulation. While beam testing represents definitive evidence of a processor's susceptibility to radiation-induced upsets, we believe that low-cost in-house bit error injection tests provide a valuable tool both in their own right and as an intermediate step towards approximating a processor or application's behavior in the presence of cosmic radiation, prior to beam testing. In this paper we describe a new hardware/software tool named the Memory Sentinel and Injection System (MSIS) that initially targets the two PowerPC 405s within the Xilinx Virtex-4 FX family of FPGAs. The MSIS leverages the configurable logic of an FPGA as well as a custom software interrupt to inject bit errors into the full set of a processor's registers and caches in a user-transparent fashion. By using the second PowerPC as a monitor, the MSIS is capable of performing rapid and unattended fault injection. Through 20,000 injections we demonstrate the impact of the MSIS on a sample sensor-like application and analyze its behavior in the presence of upsets.

As FPGA resources continue to increase, FPGAs present attractive features to the High Performance Computing community. These include the power-efficient computation and application-specific acceleration benefits, as well as tighter integration between compute and I/O resources. This paper considers the ability of an FPGA to address another, increasingly important, feature - resiliency. Specifically, a minimally-invasive monitoring infrastructure operating over a sideband network is presented. This includes a multi-chip protocol, IP cores that implement the protocol, and a tool to instrument existing hardware accelerator FPGA designs. To demonstrate the functionality, the system has been implemented on a cluster of FPGA devices running off-the-shelf MPI and Linux. We demonstrate the ability to do integrated software and hardware accelerator check pointing with restart under a variety of injected faults.

We present and describe Torc - (Tools for Open Reconfigurable Computing) - an open-source infrastructure and tool set, provided entirely as C++ source code and available at http://torc.isi.edu. Torc is suitable for custom research applications, for CAD tool development, and for architecture exploration.

This paper presents a prototype autonomous signal processing system on a chip. The system is architected such that high performance digital signal processing occurs in the FPGA¿s configurable logic, while resulting higher level data products are monitored by cognitive algorithms residing on an embedded processor. The cognitive algorithms develop situational awareness about the platform¿s environment, and use this information to modify and tune signal processing in real-time using active partial reconfiguration. This system was realized on a Xilinx Virtex4 FX 100 device on a pulse parameter measurement application utilizing a Bayesian Network cognitive algorithm. Changes in the RF environment were correctly detected 96.7% of the time and mitigation filters which resulted in at least 3dB interference rejection improvement were instanced 81% of the time. This system realizes a 71.4× reduction in size compared to static implementations and a 26-43× reduction in reaction times compared to human in the loop systems.

This paper introduces the low-power intelligent tool environment (LITE), an object oriented tool set designed for power visualization, analysis, and optimization. These tools leverage an established FPGA design environment, JHDL, that allows design logic and power utilization to be displayed, analyzed, and cross-probed simultaneously at a level of abstraction close to the design entry point. Circuit logic, FPGA architecture and power information are correlated to create accurate power prediction and estimation models. These models and power analysis tools can then be used to create power optimization algorithms. Power optimization algorithm development is supported through the use of tools to query and sort circuit characteristics and drop in COTS CAD tool compliant constraints. These constraints can be used to guide the COTS placement and routing tools to optimize for power

In this paper we outline a methodology and tool suite capable of modeling the power consumption of an FPGA design at the post synthesis, or EDIF, level. Modeling at this level has the following advantages: 1) early power feedback in the design flow, 2) power results displayed at a high level, closer to the logical design entry point 3) and the elimination of bulky, low-level timing accurate simulation and stimulus files. These three aspects allow a designer to quickly and easily generate power estimates, relate the results back to their original logical level design entry, and explore design trade-off scenarios. The results presented here were derived using Xilinx Virtex2 FPGAs and tool suites, however the techniques apply to all FPGAs.

Adaptive computing systems use FPGAs for custom hardware acceleration in high performance and real-time applications. Unlike single purpose dedicated hardware approaches, the reusable nature of the technology introduces system design tradeoffs that must balance processing density, memory, and I/O bandwidth, not to mention more subtle issues such as ease of programming, debugging, and physical integration into real-world systems. This paper describes results from the DARPA-funded SLAAC project, which developed three generations of adaptive computing systems for a diverse set of challenging signal processing applications.

The mission of the Systems-Level Applications of Adaptive Computing (SLAAC) project is to design and implement a distributed adaptive computing systems architecture. This systems-level focus of SLAAC resulted from the realization that scalability and portability are the two main obstructions preventing innovative Adaptive Computing Systems (ACS) research from being directly useful in deployed real-time environments. Scalability is an issue in that many real-world applications are larger than the modern PCI-based FPGA accelerator. Transitioning from a small proof of concept demonstration to large real-world application is often overlooked in ACS research. Portability has both a hardware and software aspect. Physical form-factor and operating system issues can limit the utility ACS research done in the lab with desktop PCs unless there is a development path to more traditional real-time environments. The SLAAC project seeks to remedy these issues of scalability and portability in ACS systems.