Time sensitive network applications, for example in Intra-Vehicular Networks, aim to give predictable end-to-end latency guarantees. As a consequence, processing resources of involved host systems remain partially unused, because they are reserved for rare worst cases. This circumstance provides the opportunity to reduce dimensioning overheads by managing the load on the nodes flexibly within the network. In our proposed approach, a SmartNIC involving an FPGA-based load balancer achieves dynamic routing of flows whilst preserving end-to-end latency guarantees. A flow-oriented online network measurement component continuously supervises network traffic with regards to compliance to flow specifications and constraints such as bounded one-way delay, absence of packet loss, and jitter. We use the supervisor to enhance forwarding decisions on the data plane. Initial evaluation yields a saving potential of around 30 %. We showcase quick dynamic reconfiguration of the FPGA when triggered by real-time measurement of the one-way delay using realistic automotive network traffic.

In this work, authors present a Hardware based strategy for IEEE802.1CB Network Reliability embedded in Automotive Gateways (GW). It is a new approach for HW efficient and cost-effective integration of Frame Replication and Elimination for Reliability (FRER) algorithm within automotive Network-on-Chip / System-on-Chip. In essence, it is a HW architecture that permits to manage the complex integration of IEEE802.1CB within In-Vehicle Networks. The FRER algorithm is split into smaller functionalities which are allocated across the different processing stages of the GW, maximizing device and network performance. The proposed architecture has a strong focus on Functional Safety, introducing important enhancements to overcome IEEE802.1CB limitations identified in the state of the art: data content verification, meaningful network diagnosability and performance verification. It moves a step forward towards fail operational systems and the compliance with ISO 26262, contributing to future autonomous driving networking solutions.

Driver assistance, self-driving, and multimedia systems have two common implications: increasing demand on network bandwidth and the need for more powerful computation nodes. As a result, intra-vehicular networks (IVNs) change their layout. They are built around central nodes connected to the rest of the vehicle via Ethernet. The usage of Ethernet presents a challenge, as it lacks support for deterministic behavior by design. The solution is found within the IEEE Time-Sensitive Networking (TSN) standards, introducing real-time, low-latency, and deterministic communication into the Ethernet ecosystem. These new networked systems need to be thoroughly evaluated with IVN requirements in mind. To assess numerous configurations of IVN setups, in this work, we introduce a novel Environment for Generic In-vehicular Networking Experiments — EnGINE. It allows, among many others, repeatable, reproducible, and replicable TSN experiments with high precision and flexibility, which is not possible to run using proprietary solutions. EnGINE is based exclusively on commercial off-the-shelf components and is orchestrated by a flexible Ansible framework. This approach allows us to configure various topologies emulating realistic IVNs behavior, which is challenging using simulations. Based on available related work, we further address the challenges found in the IVNs. We derive additional requirements for experiments in the TSN domain and present our approach to fulfill them in an experimental setting. We believe that EnGINE provides the ideal environment for TSN network experiments.

Ethernet is increasingly used in areas where time-critical and safety-relevant data are transported over the network along with best-effort flows, for example in intra vehicle networks or industrial networks. The resulting complex network architectures, time-sensitive networking configurations and system interactions are hard to foresee during the design phase. Therefore, it is hard to rule out any violations of flow specifications or timing and reliability requirements, especially in the presence of unpredictable failures.

In this work we introduce the concept of Elastic Queueing Engine (EQE) for Time Sensitive Networking (TSN) which is a new networking-optimized queueing strategy designed to maximize Quality of Service (QoS) and usability of resources in time sensitive networks. The proposed dynamic run-time adaptation of queues to network status exploits usability of resources by introducing three new degrees of elasticity in Hardware (HW), i.e., the system is able to dynamically adapt to events in incoming traffic by optimizing the usage of available resources. The three new degrees of elasticity introduced by EQE are: dynamic queues size, dynamic Internal Priority Value (IPV) management and dynamic Gate Control List (GCL). Apart from inventing the queueing closed-loop control algorithms, EQE synthesizes these three functionalities in HW as co-processors attached to the system CPU to guarantee a real-time response to ingress frames, aimed at contributing towards fail-safe and fail-operational In-Vehicle Network (IVN) solutions. Our results show that as long as there is available memory in the system, EQE for TSN can completely avoid frame drops in scenarios where static queues systems would be compromised, while other network KPIs (maximum latency, cost) remain similar to implementations without the proposed new features.

This paper describes the architecture and design flow of a self-reconfigurable embedded system, mapped on a Spartan-3 low-cost FPGA, where a fixed area is reserved to accommodate a reconfigurable coprocessor. Spartan-3 low-cost family lacks of the ICAP (Internal Configuration Access Port) and design tools for self-reconfiguration. The paper also deals with other issues, such as OPB isolation, bit-stream retrieve from external SRAM, bit-stream processing, and clock routing.

The uniqueness of human fingerprints has been accepted by the scientific community since long time ago. Proof of this is the fact that, among all physiological characteristics, fingerprints are the oldest and most deeply used signs of identity for personal recognition. However up to date, the development of an automatic fingerprint-based human authentication system is an open research problem. Most of the difficulties rely on the complexity and the high computational power needed to develop a fingerprint matching algorithm reliable enough to guarantee the accuracy of the result even when only low-quality fingerprint impressions are available from the users. In order to deal with the processing power requested by the system, an application-specific hardware accelerator developed by means of hardware-software co-design techniques is suggested in this work for the fingerprint alignment stage. The hardware processor permits to speed up the alignment phase and to reach real-time performance, which is not guaranteed when developing the same algorithm under a purely-software platform.

In the field of real-time signal processing, like most of automatic control systems nowadays present at the industry and focused on PID (proportional-integral-derivative) controllers, it is common to find software-oriented solutions based on powerful 32-bit DSP, RISC or CISC processors. This work deals with the hardware/software co-design of a PID coprocessor, all embedded on a system-on-chip device. The performances reached by a platform composed of an 8-bit MCU and a dynamically reconfigurable FPGA allow scheduling the PID algorithm as a set of tasks executed by both devices concurrently. Moreover, thanks to the flexible hardware characteristics, some modules synthesized into the FPGA are reconfigured at run-time while the rest keeps on active. This cost-effective approach, encouraged by its parallelism, is an alternative to commercial -both general-purpose and specific-purpose-processors in whatever made-to-measure engineering application