This paper presents techniques to include the effect of supply voltage noise on the circuit propagation delay of a digital VLSI circuit. The proposed methods rely on an input-independent approach to calculate the logic gate's worst-case power supply noise. A quasi-static timing analysis is then applied to derive a tight upper-bound on the delay for a selected path with power supply noise effects. This upper-bound can be further reduced by considering the logic constraints and dependencies in the circuit. Experimental results for ISCAS-85 benchmark circuits are presented using the techniques described in the paper. HSPICE simulation results are also used to validate our work.

With each technology generation, delivering a time-varying current with reduced nominal supply voltage variation is becoming more difficult due to increasing current and power requirements. The power delivery network design becomes much more complex and requires accurate analysis and optimizations at all levels of abstraction in order to meet the specifications. We describe techniques for estimation of the supply voltage variations that can be used in the design of the power delivery network. We also describe the decoupling capacitor hierarchy that provides a low impedance to the increasing high-frequency current demand and limits the supply voltage variations. Techniques for high-level power estimation that can be used for performance vs. power trade-offs to reduce the current and power requirements of the circuit are also presented.

Article Share on Maximum voltage variation in the power distribution network of VLSI circuits with RLC models Authors: Sudhakar Bobba Sun Microsystems Inc., 901 San Antonio Road, M/S: USUN02-301, Palo Alto, CA Sun Microsystems Inc., 901 San Antonio Road, M/S: USUN02-301, Palo Alto, CAView Profile , Ibrahim Hajj Department of ECE, American University of Beirut, Beirut, Lebanon Department of ECE, American University of Beirut, Beirut, LebanonView Profile Authors Info & Claims ISLPED '01: Proceedings of the 2001 international symposium on Low power electronics and designAugust 2001 Pages 376–381https://doi.org/10.1145/383082.383186Online:06 August 2001Publication History 5citation262DownloadsMetricsTotal Citations5Total Downloads262Last 12 Months1Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

In this paper, we present high-performance bidirectional repeaters that recondition the signal waveform and reduce the signal degradation. We also present the application of these repeaters to the design of high-performance bidirectional busses. SPICE simulation results for long bidirectional interconnects show an almost linear increase in delay with repeaters compared to a quadratic increase in delay without repeaters. These repeaters are also applied to improve the performance of long AND domino gates. SPICE simulation results show a significant reduction in the delay of long AND domino gate with repeaters.

Estimates of the peak power dissipation and the peak current are required in the design of reliable VLSI circuits. The peak current current drawn by a digital filter is dependent on the filter coefficients and the inputs to the multipliers in the filter. This input dependence makes the estimation of peak current for a digital filter a hard problem. We present a technique to estimate the maximum current drawn by a digital filter. The approach consists of: (1) building peak current macro-models for multipliers in terms of the input data transitions and the coefficient, and (2) using these models in a graph based formulation for finding the peak current of the digital filter. The peak current macro-models for multipliers are validated by comparisons with SPICE simulations. We also present the application of the technique for estimating the peak current of digital filters in a 51.84 Mb/s 16-CAP receiver.

In this paper, we present simulation techniques to estimate the worst-case voltage variation using an RC model for the power distribution network. Pattern independent maximum envelope currents are used as a periodic input for performing the frequency-domain steady-state simulation of the linear RC circuit to evaluate the worst-case instantaneous voltage drop for the RC power distribution networks. The proposed technique unlike existing techniques, is guaranteed to give the maximum voltage drop at nodes in the RC power distribution network. We present experimental results to compare the frequency-domain and time-domain simulation techniques for estimating the maximum instantaneous voltage drop. We also present frequency domain sensitivity analysis based decoupling capacitance placement for reducing the voltage variation in the power distribution network. Experimental results on circuits extracted from layout are presented to validate the simulation and optimization techniques.

In this paper, we present low-power and high-performance logic gates called the current-mode threshold logic (CMTL) gates. Low-power dissipation is achieved by limiting the voltage swing on the interconnects and the internal nodes of the CMTL gates. High-performance is achieved by the use of transistor configurations that sense a small difference in current and set the differential outputs to the correct values. The realization of NAND, NOR, AND, OR logic gates and other logic functions using the CMTL gates is presented. We also present several implementations of CMTL gates and describe the relative advantages and limitations of these implementations. SPICE simulation, results for a 1.5 V 0.18 u CMOS technology are also presented for the different circuit configurations described in the paper.

Programmable logic array (PLA) is a circuit realization for the two-level sum of products representation of a multi-output Boolean function. The current drawn by a PLA is input dependent and it makes the problem of estimating the maximum current intractable. Integrated circuit reliability and signal integrity are related to the maximum current drawn by the circuit. Hence, an estimate of the maximum current is required for the design of a reliable VLSI circuit. In this paper, we present an input pattern-independent algorithm to obtain the estimate of maximum and minimum currents drawn by a PLA over all possible input vectors. Experimental results on several benchmark circuits and comparisons with exhaustive simulations are also included in this paper.

In this p ap er we pr esent an inputpattern independent method to compute the maximum current envelope, which is an upper bound over all possible curr ent waveforms drawn by a circuit. The maximum current envelope can be used to compute the worst-c ase RMS current and average cur rent dr awn by a set of gates. These current values can be used in the design of the p ower bus to ensure that the power bus interconne cts are not susc eptible to ele ctromigration (EM) induced failur e. We also present comparisons with exhaustive/long simulations for MCNC/ISCAS-85 benchmark circuits to verify the accuracy of the method.