Simulation by random vectors is meaningful only if the vectors meet certain requirements on the environment that drives the design under verification. When that environment is modeled by constraints, we face the problem of solving constraints efficiently. We present an efficient algorithm for simplifying conjunctive Boolean constraints defined over state and input variables, and apply it to constrained random simulation vector generation using binary decision diagrams (BDDs). The method works by extracting "hold-constraints" from the system of constraints. Hold-constraints are deterministic and trivially resolvable. They can be used to simplify the original constraints as well as refine the conjunctive partition. Experiments demonstrate significant reductions in the time and space required for constructing the conjunction BDDs, and the time spent in vector generation during simulation.

Modeling design environment with constraints instead of a traditional testbench is advantageous in a hybrid verification framework that encompasses simulation and formal verifica-tion. This movement is gaining popularity in industry and sparks research in the constraint-based environment mod-eling and stimulus generation problem. We present an ap-proach, called constraint synthesis, to this problem. Con-straint synthesis falls in the general category of parametric Boolean equation solving but is novel in utilizing don’t care information unique to hardware constraints and heuristic variable removal to simplify the solution. Experimental re-sults have demonstrated the effectiveness of the proposed approach.

We present an algorithm for simplifying the solution of conjunctive Boolean constraints of state and input variables, in the context of constrained random vector generation using BDDs. The basis of our approach is extraction of "hold-constraints" from constraint system. Hold-constraints are deterministic and trivially resolvable; in addition, they can be used to simplify the original constraints as well as refine the conjunctive partition. Experiments demonstrate significant reduction in the time and space needed for constructing the conjunction BDDs, and the time spent in vector generation during simulation.

Digital design at Motorola is performed at design centers throughout the world, on projects with different design objectives, executed on different time scales, by different sized teams with different skill sets. This paper attempts to categorize these diverse efforts and identify common threads: what works, what the challenges are, and where we need to go.