A true random number generator (TRNG) is a fundamental component of hardware security. Latch-based TRNGs (LTRNGs), with their simple circuitry, are well-suited for energy-constrained IoT devices. However, a mismatch between the two inverters in the latch can result in little or no entropy output. This work presents chip measurement results demonstrating the use of negative bias temperature instability (NBTI) to mitigate mismatch in LTRNG. We propose a sequence to quantify the initial mismatch and selectively applying NBTI stress to PMOS device with higher conductivity for the first time. Measurement results in a 130nm CMOS process show that after 1000 minutes of NBTI stress at 3.0 V/120°C, the mismatches are reduced to within the overcompensated target of ±20 mV, and the output entropy improves from zero to over 0.85. Mismatch recovery at 20°C is negligible. Recovery at 120°C is accelerated, with mismatches still remaining below 50% of their initial values, and the output entropy remaining at 0.47 and 0.80 for the measured two chips. The randomness of post-processed data is validated using NIST SP 800-22 and SP 800-90B.

This paper presents a low-power supply-to-digital converter (SDC) for bio-recording system where bio-fuel-cell provides both power and sensing data. It is achieved by a supply-controlled oscillator, supply-dependent activation buffers (SDAB) with different V-thresholds, and an encoder. A 22-nm prototype chip exhibits its feasibility with a power of 0.9-2.6 pW under 0.1-0.25 V. Design methodology for minimizing power consumption and techniques of controlling buffer V-threshold are also introduced.

The demand for high energy efficiency in IoT devices continues to increase, necessitating the development of low energy consumption techniques to enhance the computation performance of these devices. In this study, we present a CMOS clock generator that operates at high operating voltage, achieves low frequency, and exhibits low power (LP) consumption, thus obviating the need for scaling-unfriendly step-down converters. The avoidance of step-down converters, which require passive components in their design, facilitates the development of scaling-friendly IoTs. The architecture of the prototype chip is composed of a voltage stacking and charge recycling design, which is achieved by the implementation of stacked oscillator and multiple frequency dividers in a configuration. The fabrication of the prototype chip is conducted using a 65-nm CMOS process. This work presents two configurations that are based on the concept of voltage stacking. The first configuration prioritizes LP consumption, yielding a clock generation of 2.09 Hz with a power of 0.22 nW at a voltage supply of 1.2 V and an operating range of 1.2–2.2 V. Notably, this configuration represents the lowest power achieved at a foundry-recommended nominal voltage in a sub-10-Hz clock generator. Another configuration is oriented toward generating low-frequency output signals, and the test chip attains an output frequency of 0.079 Hz and a supply voltage range of 0.88–1.3 V. The proposed architecture exhibits potential benefits in advanced technology nodes, particularly in the context of technology scaling.

True random number generators (TRNGs) are commonly used in hardware security for secure authentication, data encryption, etc. The raw random numbers often exhibit defects. The most commonly observed defects are bias and correlations. Post processing techniques have been developed to address them. The von Neumann method addresses bias, but it requires input that is uncorrelated and has an identical distribution. On the other hand, the Markov chain can address correlation but introduce bias. In this work, we research the lightweight combination of two techniques. We verified that MKV2(QL4)/VN2 performs well for both Markov and non-Markov model bitstreams. MKV1(QL8)/VN8W is effective for the Markov model. The randomness is verified by NIST SP 800-22 and 800-90B, and ENT, respectively. Both of these circuits require only 16 bits of memory, which is 12 times smaller than in previous work. MKV1(QL8)/VN8W is implemented using 65-nm CMOS. A prototype chip demonstrates a minimum energy consumption of 0.149 pJ/bit at 0.45V. When applied to a latch-based TRNG, it can double the operation frequency thanks to the enhanced decorrelation. The total energy consumption is reduced by 21%.

The battery-less sensor nodes provide a solution to power and environment issues, but they face some challenges while being applied to biosensing systems, such as varying power and communication distance. This work presents a battery-less biosensing system for solar-cell-powered continuous glucose monitoring contact lenses featuring a 2.4 GHz transmitter. The modulation method combines frequency shift keying and pulse interval modulation to send radio frequency signals with two-dimensional information including the solar cell's voltage, which aims to overcome the impact of unstable solar power. The charge-pump-based energy harvester converts the solar-cell voltage above 1.8 V to achieve a transmission distance longer than 40 cm, which allows communications between contact lenses and handsets. The fabricated chip in a 65 nm CMOS process consumes 126 nW at 0.37-V supply, which is manageable by on-lens solar cells in an indoor ambient-light environment.

This work presents the first solar cell (SC)-powered biofuel cell (BFC)-input biosensing system using 65 nm CMOS with pulse interval modulation (PIM) and pulse density modulation (PDM) LED driving capability for stand-alone RF-less continuous glucose monitoring (CGM) contact lenses, which notices diabetes patients of CGM level without any external devices. LED implementation can eliminate the necessity of wireless communication. Power supply from on-lens SCs can eliminate the necessity of wireless power delivery, enabling a fully stand-alone operation under office-room ambient light.

This work presents the lowest power consumption sub-mm2 supply modulated OOK transmitter for enabling self-powered continuous glucose monitoring (CGM) contact lens. By combining the transmitter with a glucose fuel cell which functions as both the power source and sensing transducer, self-powered CGM contact lens can be emerged. The 385 x 385 μm2 test chip implemented in 65-nm standard CMOS technology operates 270pW under 0.165V and successfully demonstrates self-powered operation using 2 x 2 mm2 solid-state glucose fuel cell.

A design of gate-leakage-based timer using an amplifier-less replica-bias switching technique that can realize stable and low-voltage operation is presented. To generate stable oscillation frequency, the topology that discharges the pre-charged capacitor via a gate leaking MOS capacitor with low-leakage switch and logic circuits is employed. The test chip fabricated in 55-nm deeply depleted channel (DDC) CMOS technology achieves an Allan deviation floor of 200 ppm at a supply voltage of 350 mV in a 0.0022 mm2 area.

This paper presents a millimeter-wave frequency-shift-based CMOS biosensor that is capable of providing three-dimensional (3D) resolution. The vertical resolution from the sensor surface is obtained using dual-layer LC oscillators, which enable 3D target detection. The LC oscillators produce different frequency shifts from the desired resonant frequency due to the frequency-dependent complex relative permittivity of the biomolecular target. The measurement results from a 65-nm test chip demonstrated the feasibility of achieving 3D resolution.

A fully-integrated CMOS circuit based on a vector network analyzer (VNA) and a transmission-line-based detection window for circulating tumor cell (CTC) and exosome analysis is presented. We have introduced a fully-integrated architecture, which eliminates the undesired parasitic components and enables high-sensitivity, for analysis of extremely low-concentration CTC in blood. To validate the operation of the proposed system, a test chip was fabricated using 65-nm CMOS technology. Measurement results shows the effectiveness of the approach.

This paper presents 2D imaging using photosensor platform with a newly-proposed large-scale CMOS biosensor array in 0.6-μm standard CMOS. The platform combines photosystem I (PSI) isolated from Thermosynechococcus elongatus and a large-scale CMOS biosensor array. PSI converts the absorbed photons into electrons, which are then sensed by the CMOS biosensor array. The prototyped photosensor enables CMOS-based 2D imaging using PSI for the first time.

We present sub-1-V CMOS-based electrophoresis method for small-form-factor biomolecule manipulation that is contained in a microchip. This is the first time this type of device has been presented in the literature. By combining CMOS technology with electroless gold plating, the electrode pitch can be reduced and the required input voltage can be decreased to less than 1 V. We fabricated the CMOS electrophoresis chip in a cost-competitive 0.6 μm standard CMOS process. A sample/hold circuit in each cell is used to generate a constant output from an analog input. After forming gold electrodes using an electroless gold plating technique, we were able to manipulate red food coloring with a 0--0.7 V input voltage range. The results shows that the proposed CMOS chip is effective for electrophoresis-based manipulation.

This paper presents a self-controlled dual-oscillator-based supply voltage monitor for biofuel-cell-combined biosensing systems. First, the proposed self-triggered architecture enables self-control without requiring any external control signals. Second, the proposed frequency subtraction with two gate-leakage-based oscillators with different supply sensitivities enables low-power, small-footprint, and accurate supply voltage monitoring. The proposed supply voltage monitor converts the change in supply voltage into a digital supply voltage code. The proposed supply voltage monitor is fabricated using 65-nm CMOS technology with an active area of 0.0047 mm2, and it shows an operating supply voltage range of 250 mV (0.75-1 V). It consumes a standby power of 1.4 nW at a supply voltage of 0.75 V and has a voltage resolution of 2.4 mV. Furthermore, the measurement results show a peak-to-peak inaccuracy of +12.1 mV/-8.4 mV.

A current-integration-based CMOS amperometric sensor with a bacteria-sized (1.2 μm × 2.05 μm) electroless-plated microelectrode array for high-sensitivity bacteria counting is presented. For high-sensitivity bacteria counting with sufficient SNR, noise must be reduced because the bacteria-sized microelectrode can handle only small current on the order of nA. The proposed current integration can reduce noise associated with the CMOS sensor. Measurement results with a 0.6-μm test chip demonstrate successful high-sensitivity 2D direct counting of microbeads with 27 dB SNR.

This paper presents a time-domain biosensor array that uses a capacitor-less current-mode analog-to-time converter (CMATC) and logarithmic cyclic time-attenuation-based TDC with discharging acceleration. Combining the exponential function of the CMATC and logarithmic function of the proposed TDC offers linear input-output characteristics. The time-domain property enables bio-imaging at a high spatial resolution and large scale while maintaining scalability. Measurement results with a 0.25-μm test chip successfully demonstrated linear input-output characteristics.

This paper presents an energy-autonomous bio-sensing system with the capability of wireless communication. The proposed system includes a biofuel cell as a power source and sensing frontend associated with the integrated supply-sensing sensor. The sensor consists of a digital-based gate leakage timer, supply-insensitive time-domain temperature sensor, and inductive-coupling transmitter. A test chip using 65-nm CMOS technology was operated with a supply of 0.19 V and consumed 53 μW to successfully demonstrate wireless communication with an asynchronous receiver.

An energy-autonomous, disposable supply-sensing biosensor based on bio fuel cells and a 0.23-V 0.25-µm zero-Vth all-digital CMOS supply-controlled ring oscillator with a current-driven pulse-interval-modulated inductive-coupling transmitter was demonstrated. All-digital and current-driven architecture using zero-Vth transistors enables low-voltage operation and small footprint in cost-competitive legacy CMOS. Measured results with 0.25-µm CMOS testchip successfully demonstrated operation under a 0.23-V supply, which is the lowest supply voltage among reported proximity transmitters. An energy-autonomous biosensing operation using organic bio fuel cells was also demonstrated.

A CMOS pulsewidth modulation (PWM) transceiver circuit that exploits the self-referenced edge detection technique is presented. By comparing the rising edge that is self-delayed by about 0.5 T and the modulated falling edge in one carrier clock cycle, area-efficient and high-robustness (against timing fluctuations) edge detection enabling PWM communication is achieved without requiring elaborate phase-locked loops. Since the proposed self-referenced edge detection circuit has the capability of timing error measurement while changing the length of self-delay element, adaptive data-rate optimization and delay-line calibration are realized. The measured results with a 65-nm CMOS prototype demonstrate a 2-bit PWM communication, high data rate (3.2 Gb/s), and high reliability (BER> 10-12) with small area occupation (540 μm2). For reliability improvement, error check and correction associated with intercycle edge detection is introduced and its effectiveness is verified by 1-bit PWM measurement.

In a large-scale time-domain sensor array, propagation of the pulse voltage causes considerable pulse distortion due to a large bitline capacitance. This work demonstrates a time-domain potentiometric biosensor array with a newly-proposed 4T sensor cell and pulse processing circuit functioning as a charge-conserved analog-to-time converter (CCATC) that converts from input analog voltage to a pulse current. By employing the pulse current with the fixed bitline voltage, short-pulse detection with high energy efficiency becomes possible. Simulation results for 600-nm CMOS technology demonstrate the detection of a 10-ns pulse, even with a large bitline capacitance of over 10 pF.

Design of a clock jitter reduction circuit that exploits the phase blending technique between the uncorrelated clock edges that are self-delayed by multiples of the clock cycle, nT is presented. By blending uncorrelated clock edges, the output clock edges approach the ideal timing and, thus, timing jitter can be reduced by a factor of √2 per stage. There are three technical challenges to realize this: 1) generating uncorrelated clock edges, 2) phase averaging with small time offset from the ideal center position, and 3) minimizing the error in nT-delay being deviated from ideal nT. The proposed circuit overcomes each of these by exploiting an nT-delay, gated phase blending, and self-calibrated nT-delay elements, respectively. Measurement results with a 180-nm CMOS prototype chip demonstrated an approximately four-fold reduction in timing jitter from 30.2 ps to 8.8 ps in 500-MHz clock by cascading the proposed circuit with four-stages.

This paper demonstrates a reference-free, high-resolution on-chip timing jitter measurement circuit. It combines a self-referenced clock and a cascaded time difference amplifier (TDA), which results in reference-free, high-resolution timing jitter measurement without sacrificing operational speed. The test chip was designed and fabricated in 65 nm CMOS. Measured results of the proposed circuit show the possibility of detecting a timing jitter of 1.61-ps RMS in 820 MHz clock with less than 4% error.

This paper describes algorithms for generating low intermodulation-distortion (IMD) two-tone sinewaves, for communication application ADC testing, using an arbitrary waveform generator (AWG) or a multi-bit ΣΔ DAC inside an SoC. The nonlinearity of the DAC generates distortion components, and we propose here eight methods to precompensate for the IMD using DSP algorithms and produce low-IMD two-tone signals. Theoretical analysis, simulation, and experimental results all demonstrate the effectiveness of our approach.

This paper reviews the theory and introduces the architecture for a clock source with low phase noise and for measuring timing jitter. This approach utilizes a sample mean and sum of two random variables, and can be implemented in CMOS or SiGe BiCMOS circuits.

This paper proposes a new procedure for calculating high-accuracy PDF estimates, which are free of random error and nearly free of bias error. The procedure is verified experimentally using random jitter and a 16-bitADC.

This paper presents a low-power inductive-coupling link in 90-nm CMOS. Our newly proposed transmitter circuit uses a charge-recycling technique for power-aware 3-D system integration. The cross-type daisy chain enables charge recycling and achieves power reduction without sacrificing communication performance such as a high timing margin, low bit error rate and high bandwidth. There are two design issues in the cross-type daisy chain: pulse amplitude reduction and another is inter-channel skew. To compensate for these issues, an inductor design and a replica circuit are proposed and investigated. Test chips were designed and fabricated in 90-nm CMOS to verify the validity of the proposed transmitter. Measurements revealed that the proposed cross-type daisy chain transmitter achieved an energy efficiency of 65 fJ/bit without degrading the timing margin, data rate, or bit error rate. In order to investigate the compatibility of the transmitter with technology scaling, a simulation of each technology node was performed. The simulation results indicate that the energy dissipation can be potentially reduced to less than 10 fJ/bit in 22 nm CMOS with proposed cross-type daisy chain.

In this paper, we report the world's first ac-coupled clock distribution circuit for low-power and high-frequency clock distribution. By employing the proposed ac-coupled LC-based voltage-controlled oscillator (LC-VCO) and phase interpolators, the use of conventional current-mode-logic (CML) buffers with large power requirements can be prevented, and power consumption for clock distribution can be reduced. With the aim of verifying the effectiveness of the proposed circuit, test chips were designed and fabricated in 0.18-$\mu$m mixed-signal CMOS technology. The measured results indicated a 14.007 GHz clock distribution to four points whose pitches are 450$\mu$m, with 6.9 mW of power. The phase noise was measured to be$-$79.06 dBc/Hz at a 100 kHz offset,$-$101.66 dBc/Hz at a 1 MHz offset, and$-$107.25 dBc/Hz at a 10 MHz offset, with a clock frequency of 12.96 GHz. Furthermore, a phase averaging technique for reducing phase deviation was proposed and theoretically investigated.

This paper discusses analysis and techniques for mitigating interference of an inductive-coupling inter-chip link. Electromagnetic interference from power/signal lines and to SRAM circuits was simulated and measured. In order to verify the interference, test chips were designed and fabricated using 65-nm CMOS technology. The measurement results revealed that: 1) interference from power lines depends on the shape of the power lines; 2) interference from signal lines can be canceled by increasing transmitter power by only 9%; and 3) interference with SRAM circuits is less important than other issues under ordinary conditions. Based on the measurement results, interference mitigation techniques are proposed and investigated.

Modeling and experimental verification of misalignment tolerance in inductive-coupling inter-chip links for 3-D system integration is introduced for the first time. Misalignment between stacked chips reduces coupling coefficiency of on-chip inductors and increases transmitter power. We proposed a modeling which estimates the increase in transmitter power by considering misalignment as an additional communication distance. Proposed model was verified by electromagnetic simulations and by measurements using testchips fabricated in 65-nm CMOS technology. The results calculated by the proposed modeling match well with measurement results. Measurement results show that misalignment tolerance of inductive-coupling link is well high and can be ignored in common conditions.

MuCCRA-Cube is a scalable three dimensional dynamically reconfigurable processor. By stacking multiple dies connected with inductive-coupling links, the number of PE array can be increased so that the required performance is achieved. A prototype chip with 90nm CMOS process consisting of four dies each of which has a 4 × 4 PE array was implemented. The vertical link achieved 7.2Gb/s/chip, and the average execution time is reduced to 31% compared to that using a single chip.