This paper describes an automatic partitioning and placement system for CMOS gate arrays utilizing two different kinds of data: circuit structure and hierarchical design data. Characteristic circuit structures such as the bus structure and the iterative structure are automatically extracted and handled like single cells in the placement process. The partitioning process has employed two processes: one is the bottom-up extraction of these structures, and the other is the top-down process, which divides the given circuit into several subcircuits. Making use of the partitioning results, the placement program is also carried out by two-level processes: subcircuit-level placement and cell-level placement. Through experiments, it has been proved that the proposed technique is effective for attaining better layout results.