A symbolic cell generator (SYC) that can generate the symbolic layout of a generic CMOS logic cell is presented. It accepts as input a SPICE-like netlist describing circuit components, connectivity, and the list of the I/O pins. Using this generator, the user can specify topological constraints on pin and transistor positions, the maximum lengths of polysilicon and diffusion wires, and a preferred layer for each electrical node. Cells are generated according to optimization criteria that take into account not only geometric factors, such as cell area, aspect ratio, and wirelength, but also electrical features, namely capacitance to the substrate and contact and via minimization. The generator's placement strategy includes transistor clustering into regions, global region placement by linear ordering, and two-dimensional local transistor placement. The routing combines Steiner trees and Lee algorithms. Object-oriented programming paradigms were used in the implementation of the program, written in C++ language. Experimental results for small and medium-sized cells are presented.>

A general methodology, based on the concept of folding, for mapping wavefront algorithms into processor square meshes of fixed size has been implemented on a mesh of INMOS transputers, programmed in OCCAM, for the multiplication of matrices of arbitrary size. Different implementations of the code are considered and compared. The computational costs are analyzed in detail. The method and the performances of the system used are compared with other more standard solutions.>

A router based on a tile-expansion algorithm and corner stitching data structure is presented. This program finds connections with a minimum number of jogs and it ensures that a possible solution will be found. Using a working tree, it allows an exhaustive and recursive search along all available areas for routing. The connections are made going back through the working tree until the starting terminal is reached. There are two Manhattan layers that the user can choose for each direction to implement connections; the router can be used to wire hierarchical blocks using a chip planning methodology. The program has been successfully tested on examples concerning different classes of problems.