A longstanding goal of neuromorphic computing is to develop novel computer architectures with a brain-like energy footprint. Still, key biological components such as dendrites are often overlooked. Instead, more compact scalable neuron models are favored for neuromorphic implementations. Here we present a novel neuroscience-inspired multiplicative circuit that uses shunting inhibition as the multiplicative mechanism in a CMOS dendrite circuit. We demonstrate an experimental implementation of our model on a 350-nm process field programmable analog array (FPAA) integrated circuit (IC), that exhibits shunting inhibition as a multiplicative process in neuromorphic circuits.

A robot's motion planner should find a path from its current location to its goal in an optimum way, where optimality in this paper is the shortest path. This paper proposes a new method of decision making using a phase delay technique. The robot's workspace is converted into a resistive-capacitive grid network, and the path is found by measuring and comparing the propagation times for a signal from the goal to the robot's next possible positions. A reconfigurable AVLSI architecture based on floating-gate transistors is proposed and simulation results with analytical complexity analysis equations are presented to describe the algorithm's performance. Finally, results from a robot hardware-in-the-loop platform are presented.

This paper presents path planning using reconfigurable analog very large scale integrated (AVLSI) circuits. Existing research has shown that custom AVLSI circuits known as application specific integrated circuits (ASICs) can theoretically be used for path planning. There are two main drawbacks to using custom ASICs: 1) circuit designs are fixed to some extent (not changeable) and 2) long design cycle/fabrication time (order of months). Reconfigurable analog circuits called field-programmable analog arrays (FPAAs) have been used to implement a variety of AVLSI circuits in a short time (order of minutes). This paper presents an algorithm for mapping a robot's environment onto an FPAA, and then presents hardware results using an FPAA to implement the path-planning algorithm. Experimental results and analysis are presented for 24 environment scenarios. Digital search methods like breadth-first search have solutions which scale on the order of O(4d) whereas this paper will show our analog solution is on the order of O(d) where d is the depth of the solution.

This demonstration presents live hands-on experience of the System on Chip (SoC) large-scale Field Programmable Analog Array (FPAA) IC [1] through a complete PC Board and high-level tool interface [2]. Figure 1a shows the demonstration requires only basic power connection to the laptop. The hardware includes an FPAA demonstration board and a Digilent USB device to enable a scope / function generator functionality.

The Scale Invariant Feature Transform (SIFT) is an algorithm for describing local features in an image. This research successfully demonstrates a model for optimizing SIFT using block convolution pre-filtering. A method is presented which theoretically reduces SIFT run time by nearly 50% by greatly limiting the area of image regions required to search for SIFT features. The block convolution of an image is computed using a kernel designed to be predictive of potential regions of interest. The performance of several different types of kernels are compared, most of which were produced using an evolutionary search algorithm. The filtered image is used to locate the potential regions of interest and mask regions that are unlikely to produce matches. This model will provide the framework for an optimized hardware implementation of SIFT in scenarios requiring low power and high speed, such as a robotic computer vision system. The advantage of the model lies in the very low computational intensity required to mask areas of the image where a match is unlikely to be found, yielding a more efficient implementation of SIFT.

This paper presents hardware results for a neuromorphic approach to path planning using a neuron array integrated circuit. The algorithm is explained and experimental results are presented showing 100% correct and optimal performance for a large number of randomized maze environment scenarios. Based on neuron signal propagation speed, neuron integrated circuit (IC) path planning may offer a computational advantage over state-of-the-art wavefront planners implemented on field-programmable gate arrays (FPGAs). Analytical time and space complexity metrics are developed in this paper for a neuron ICs planner, and these are verified against experimental data. Optimality and completeness are also addressed. The neuron structure allows one to develop sophisticated graphs with varied edge weights between nodes of the grid. Two interesting cases are presented. First, asymmetric edge costs are assigned to describe cases, which have a certain cost to travel a path in one direction, but a different cost to travel the same path but in the opposite direction. The application of this feature can translate to real world problems involving hills, traffic patterns, and so forth. Second, cases are presented where the nodes near an obstacle are given higher costs to visit these nodes. This is in an effort to keep the autonomous agent at a safe distance from obstacles. This grid weighting can also be used to differentiate among terrains such as sand, ice, gravel, or smooth pavement. Experimental results are presented for both cases.

We present the successful application of reconfigurable Analog-Very-Large-Scale-Integrated (AVLSI) circuits to motion planning for the AmigoBot robot. Previous research has shown that custom application-specific-integrated-circuits (ASICs) can be used for robot path planning. However, ASICs are typically fixed circuit designs that require long fabrication times on the order of months. In contrast, our reconfigurable analog circuits called Field Programmable Analog Arrays (FPAAs) implement a variety of AVLSI circuits in minutes. We present experimental results of online robot path planning using FPAA circuitry, validating our assertion that FPAA-based AVLSI design is a feasible approach to computing complete motion plans using analog floating-gate resistive grids. We demonstrate the integration of FPAA hardware and software with a real robot platform and hardware in the loop simulations, present the trajectories developed by our planner and provide analysis of the time and space complexity of our proposed approach. The paper concludes by formulating metrics that identify domains where analog solutions to planning may be faster and more efficient than traditional, digital robot planning techniques.

This paper presents preliminary results of a mobile manipulator robot tasked to play the classic Towers of Hanoi game. We first discuss the control algorithms necessary to enable necessary game-playing behavior and provide results of implementing our methodology in a high fidelity 3D environment. After attaining success in the simulation environment, we provide results on implementation of the same control software using physical robot hardware. Additionally, preliminary analysis for implementing analog Proportional-Integral-Derivative (PID) control on this platform using a floating-gate based reconfigurable analog IC is explored. Using this concept of floating gate analog arrays for control enables off-loading of the processing, which could be helpful for real-time implementation of robot behavior.

Analog circuits and systems research and education can benefit from the flexibility provided by large-scale Field Programmable Analog Arrays (FPAAs). This demonstration will present visitors with the hardware and software infrastructure supporting the use of a family of floating-gate based FPAAs being developed at Georgia Tech. A picture of the programming and control hardware that will be demonstrated is found in Figure la. Figure lb shows the software flow that will be demonstrated. The infrastructure is compact and portable and provides the user with a comprehensive set of tools for custom analog circuit design and implementation. The infrastructure includes the FPAA integrated circuit (IC); discrete analog to digital converters (ADC), digital to analog converters (DAC) and amplifier ICs; a 32-Bit ARM based microcontroller (μC) for interfacing the FPAA with a laptop computer; and Matlab and targeting software. The FPAA hardware communicates with Matlab over a Universal Serial Bus (USB) connection. The USB connection also provides the hardware's power. The software tools in the demonstration include three major systems: a Matlab Simulink FPAA program, a SPICE to FPAA compiler called GRASPER, and a visualization tool called RAT. Figure 2 shows a block diagram of the Programming and Control board and demonstration setup.

Analog circuits and systems research and education can benefit from the flexibility provided by large-scale Field Programmable Analog Arrays (FPAAs). This paper presents the hardware and software infrastructure supporting the use of a family of floating-gate based FPAAs being developed at Georgia Tech. This infrastructure is compact and portable and provides the user with a comprehensive set of tools for custom analog circuit design and implementation. The infrastructure includes the FPAA IC, discrete ADC, DAC and amplifier ICs, a 32-Bit ARM based microcontroller for interfacing the FPAA with the user's computer, and Matlab and targeting software. The FPAA hardware communicates with Matlab over a USB connection. The USB connection also provides the hardware's power. The software tools include three major systems: a Matlab Simulink FPAA program, a SPICE to FPAA compiler called GRASPER, and a visualization tool called RAT. The hardware consists of two custom PCB designs which include a main board used to program and control an FPAA IC and an FPAA IC adaptor board used to interface a QFP packaged FPAA IC with the 100 pin ZIF socket on the main programming and control board.

This paper presents our programmable floating-gate dendrite model based upon our transistor channel models. We are developing a flexible, low-power, real-time computational engine for studying, understanding, and implementing neural computation. Here we present a systematic study of the dynamics seen in this silicon model, emphasizing the connection to conventional neurobiological modeling of dendrites. These results provide a foundation for future work on larger systems.

Recently the authors presented transistor channel models of biological channels and the resulting implementation towards building spiking nodes, synapses, and dendrites. The authors also discussed how to build reconfigurable dendrites using programmable analog techniques. With all of this technology components available, the authors begin to address the question of the computation model possible using a dendrite element, as well as a network of dendrite elements. The authors discuss the connection between a dendrite element and a hidden Markov model (HMM) classifier branch, as well as a network of dendrites and somas to create an HMM classifier typical of what is used in speech recognition systems. The authors present simulation and experimental results for the branch elements; the authors also present initial results for a small dendrite based classifier structure to show the similarities to the HMM paradigm.