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Robert Miyaoka

dblp:79/4659 · also Robert S. Miyaoka · DBLP profile ↗
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3ranked-venue papers
0as first author
0since 2021 · last 2013
0000-0001-8443-9843ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2Applied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Reconfigurable computing and FPGAs · 100%
Interdisciplinary, comprehensive, and emerging computing
2 papers
Medical and health informatics · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Reconfigurable computing and FPGAs › FPGA-based embedded system
FPGA-based data acquisition
0.222009
FPGA-based front-end electronics for positron emission tomography · FPGA 2009
Fpga-based data acquisition system for a positron emission tomography (PET) scanner · FPGA 2008
Medical and health informatics
medical imaging
0.122009
FPGA-based front-end electronics for positron emission tomography · FPGA 2009
Fpga-based data acquisition system for a positron emission tomography (PET) scanner · FPGA 2008
Medical and health informatics › medical imaging › nuclear medicine imaging
positron emission tomography
0.122009
FPGA-based front-end electronics for positron emission tomography · FPGA 2009
Fpga-based data acquisition system for a positron emission tomography (PET) scanner · FPGA 2008

Methods — techniques the papers use, named apart from their topics

pulse timing · 0.4statistical positioning · 0.2event localization · 0.2signal processing · 0.2
YearPublicationVenuePosition
2013 Multiple-Hit Parameter Estimation in Monolithic Detectors
abstract
We examine a maximum-a-posteriori method for estimating the primary interaction position of gamma rays with multiple interaction sites (hits) in a monolithic detector. In assessing the performance of a multiple-hit estimator over that of a conventional one-hit estimator, we consider a few different detector and readout configurations of a 50-mm-wide square cerium-doped lutetium oxyorthosilicate block. For this study, we use simulated data from SCOUT, a Monte-Carlo tool for photon tracking and modeling scintillation- camera output. With this tool, we determine estimate bias and variance for a multiple-hit estimator and compare these with similar metrics for a one-hit maximum-likelihood estimator, which assumes full energy deposition in one hit. We also examine the effect of event filtering on these metrics; for this purpose, we use a likelihood threshold to reject signals that are not likely to have been produced under the assumed likelihood model. Depending on detector design, we observe a 1%-12% improvement of intrinsic resolution for a 1-or-2-hit estimator as compared with a 1-hit estimator. We also observe improved differentiation of photopeak events using a 1-or-2-hit estimator as compared with the 1-hit estimator; more than 6% of photopeak events that were rejected by likelihood filtering for the 1-hit estimator were accurately identified as photopeak events and positioned without loss of resolution by a 1-or-2-hit estimator; for PET, this equates to at least a 12% improvement in coincidence-detection efficiency with likelihood filtering applied.
William C. J. Hunter, Harrison H. Barrett, Thomas K. Lewellen, Robert Miyaoka
IEEE Trans. Medical Imaging4
2009 FPGA-based front-end electronics for positron emission tomography
abstract
Modern Field Programmable Gate Arrays (FPGAs) are capable of performing complex discrete signal processing algorithms with clock rates above 100MHz. This combined with FPGA's low expense, ease of use, and selected dedicated hardware make them an ideal technology for a data acquisition system for positron emission tomography (PET) scanners. Our laboratory is producing a high-resolution, small-animal PET scanner that utilizes FPGAs as the core of the front-end electronics. For this next generation scanner, functions that are typically performed in dedicated circuits, or offline, are being migrated to the FPGA. This will not only simplify the electronics, but the features of modern FPGAs can be utilizes to add significant signal processing power to produce higher resolution images. In this paper two such processes, sub-clock rate pulse timing and event localization, will be discussed in detail. We show that timing performed in the FPGA can achieve a resolution that is suitable for small-animal scanners, and will outperform the analog version given a low enough sampling period for the ADC. We will also show that the position of events in the scanner can be determined in real time using a statistical positioning based algorithm.
Michael Haselman, Robert Miyaoka, Thomas K. Lewellen, Scott Hauck, Wendy McDougald, Don Dewitt
FPGA2
2008 Fpga-based data acquisition system for a positron emission tomography (PET) scanner
abstract
Modern Field Programmable Gate Arrays (FPGAs) are capable of performing complex discrete signal processing algorithms with clock rates of above 100MHz. This combined with FPGAs low expense, ease of use, and selected dedicated hardware make them an ideal technology for a data acquisition system for positron emission tomography (PET) scanner. Our laboratory is producing a high-resolution, small-animal PET scanner that utilizes FPGAs as the core of the front-end electronics. While this scanner uses an Altera ACEX1k and has limited complexity, we are also developing a new set of front-end electronics based on an Altera StratixII. This next generation scanner utilizes many of the features of modern FPGAs to add significant signal processing to produce higher resolution images. One such process we discuss is sub-clock rate pulse timing. We show that timing performed in the FPGA can achieve a resolution that is suitable for small-animal scanners, and will outperform the analog version given a low enough sampling period for the ADC
Michael Haselman, Robert Miyaoka, Thomas K. Lewellen, Scott Hauck
FPGA2