The continuing development of smaller electronic devices into the nanoelectronic regime offers great possibilities for the construction of highly parallel computers. This paper describes work designed to discover the best ways to take advantage of this opportunity. Simulated results are presented which indicate that improvements in clock rates of two orders of magnitude, and in packing density of three orders of magnitude, over the best current systems, should be attainable. These results apply to the class of data-parallel computers, and their attainment demands modifications to the design which are also described. Evaluation of the requirements of alternative classes of parallel architecture is currently under way, together with a study of the vitally important area of fault-tolerance.

A number of architectures which combine efficient iconic and symbolic processing are reviewed. An approach which enhances the structure of the 2D mesh while still retaining that structure is suggested. The deficiencies of the mesh, in its usual form, in terms of symbolic processing are taken as indications of how the enhancement should proceed. The authors identify three orthogonal properties (processor power, processor autonomy, and interprocessor connectivity) which are open to manipulation. On the basis of a number of generic operations, both iconic and symbolic, the effect of varying each of these parameters is examined with emphasis on the requirements for sequences of operations to execute efficiently. An attempt is made to evaluate the cost-effectiveness of the various possibilities.>

A description is given of the CLIP7 image-processing chip. The device is implemented as a custom designed integrated circuit and contains a single processing element for use in arrays of processors. The chip uses 16-bit internal and 8-bit external data buses and divides crudely into two major sections: data processing and data input/output. The first structure to be assembled using these processors is a 256-element linear array, each element incorporating two of the CLIP7 processors. This system, known as CLIP7A, is used both to study the application of partial local autonomy techniques to image processing and also as a fast and convenient system for the emulation of other architectures. CLIP7A software and hardware are also described.>

Picture processing includes a variety of algorithms employed at different stages within a recognition process. Although single parallel algorithms have been suggested, no systematic comparison with sequential algorithms is available. We propose here some parallel algorithms solving a selected set of picture-processing tasks and compare their speed, when implemented on a CLIP machine, with that of the equivalent sequential algorithms implemented on a standard minicomputer. It is shown that parallel algorithms are faster than the sequential ones by a factor depending on the size of the digitization matrix, even when arithmetical operations are widely involved.

Image processing and pattern recognition are tasks which are proving surprisingly resistant to automation. The majority of pattern recognition problems have still to be formulated in a manner sufficiently precise to allow effective programs to be written, whilst conventional approaches would seem to lead to a requirement for almost infinite processing times and storage area. Conventional serial digital computers are not well matched to the processes involved in pattern recognition. A processor composed of an array of logic elements interconnected with nearest neighbours and processing in parallel is better matched and can operate at greater speed. In order to explore fully the problems which are likely to be encountered in the use of parallel processing cellular logic arrays, several have been constructed and operated, the most recent of which, CLIP 3, is described.