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Eric Tomacruz

dblp:79/4988 · DBLP profile ↗
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2ranked-venue papers
1as first author
0since 2021 · last 1994
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
High-performance computing · 58% Electronic design automation · 35% Parallel and multicore computing · 8%
Interdisciplinary, comprehensive, and emerging computing
1 paper
Computational science and engineering · 100%

Topics — the 7 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Computational science and engineering › computational physics
semiconductor device simulation
0.011994
A parallel iterative linear solver for solving irregular grid semiconductor device matrices · SC 1994
High-performance computing › numerical linear algebra › linear solver
iterative linear solvers
0.011994
A parallel iterative linear solver for solving irregular grid semiconductor device matrices · SC 1994
High-performance computing
numerical linear algebra
0.011994
A parallel iterative linear solver for solving irregular grid semiconductor device matrices · SC 1994
Electronic design automation › technology computer-aided design
device simulation
0.011991
A massively parallel algorithm for three-dimensional device simulation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1991
Electronic design automation › technology computer-aided design › device simulation
three-dimensional device simulation
0.011991
A massively parallel algorithm for three-dimensional device simulation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1991
Parallel and multicore computing
parallel algorithms
0.011994
A parallel iterative linear solver for solving irregular grid semiconductor device matrices · SC 1994
High-performance computing
parallel numerical algorithms
0.011991
A massively parallel algorithm for three-dimensional device simulation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1991

Methods — techniques the papers use, named apart from their topics

preconditioning · 0.0partitioning · 0.0communication scheduling · 0.0ILU · 0.0CGS · 0.0partitioned natural ordering · 0.0conjugate gradient squared iteration · 0.0
YearPublicationVenuePosition
1994 A parallel iterative linear solver for solving irregular grid semiconductor device matrices
abstract
Presents the use of parallel processors for the solution of drift-diffusion semiconductor device equations using an irregular grid discretization. Preconditioning, partitioning and communication scheduling algorithms are developed to implement an efficient and robust iterative linear solver with preconditioning. The parallel program is executed on a 64-node CM-5 and is compared with PILS (a solver for ill-conditioned systems) running on a single processor. We observe an efficiency increase in obtaining parallel speed-ups as the problem size increases. We obtain 60% efficiency for CGS (a fast Lanczos-type solver for nonsymmetric linear systems) with no preconditioning for large problems. Using CGS with processor ILU preconditioning and magnitude threshold-fill-in preconditioning for the CM-5, and CGS with ILU for PILS, we attain 50% efficiency for the solution of large matrices.>
Eric Tomacruz, Jagesh V. Sanghavi, Alberto L. Sangiovanni-Vincentelli
SC1
1991 A massively parallel algorithm for three-dimensional device simulation
abstract
Based on a CGS (conjugate gradient squared) iteration with a partitioned natural ordering, a novel massively parallel algorithm for three-dimensional device simulation is presented. This algorithm requires constant time per matrix iteration independent of the number of grid nodes, and has convergence properties comparable to those of good algorithms currently used on sequential computers. This algorithm has been implemented on the Connection Machine and achieves supercomputer performance for large numbers of grid nodes. Results are presented for a wide variety of devices and mesh sizes.>
Donald M. Webber, Eric Tomacruz, Roberto Guerrieri, Toru Toyabe, Alberto L. Sangiovanni-Vincentelli
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2