This article presents an integrated quadrature balanced power amplifier (PA) operating at a 26-GHz frequency range and techniques to mitigate the frequency-dependent amplitude response of quadrature hybrids used in the balanced amplifier design. The overall structure consists of two stacked pseudo-differential PAs and transformer-based quadrature hybrids designed with 22-nm CMOS FDSOI. Two techniques to compensate frequency-dependent amplitude response of the quadrature hybrid when operating away from the center frequency are proposed. The first one involves a dual input drive and the second one involves asymmetric biasing. With distortion contribution analysis, it is shown that asymmetric biasing compensates quadrature hybrid asymmetry but also produces mutually compensating third-order nonlinearity, resulting in improved linearity. Measurements with continuous wave (CW) and high dynamic range fifth generation (5G) modulated signal demonstrate that the described techniques improve output power that can be reached within the linearity specifications when operating away from the center frequency.

To optimize the linearity of mixers, one needs to recognize the origins and mixing mechanisms of dominant nonlinearities. This article presents a time-varying (TV) nonlinear analysis, where TV polynomial models are used to yield harmonic mixing functions in four simple mixer structures. Local oscillator (LO) waveform engineering has been utilized to tailor the nonlinearity coefficients, which were later fed into a numerical distortion contribution analysis tool to calculate the nonlinearity using a Volterra series-based approach. The spectra of the nonlinear voltages have been drawn, followed by plots breaking the final IM3 distortion down into its contributions. The effect of filtering on distortion has been illustrated in the end.

Behavioral amplifier models are heavily used in system-level simulations to understand the fundamental impact of a certain kind of nonlinearity for the designed transmit and receive signals. However, every model requires an accurate set of parameters to gain realistic results, which are not often publicly available, especially for higher frequency bands at millimeter-wave and above that. This applies also to transistor models used in amplifier simulations, which are, in most cases, characterized by measurements only up to around 100 GHz. In this paper, we fit parameters of common memoryless amplifier models, such as Rapp, Ghorbani, and Saleh, against measurement and circuit-level simulation data of a 300 GHz amplifier. The derived model parameters are given such that they can be used by other researchers when studying the impacts of nonlinearity. As an example, the models are utilized to simulate error vector magnitude performance with different input and output signal powers.

Stacked MOS power amplifiers (PA) are commonly used in SOI nodes but also have the potential to be realized in bulk CMOS nodes. In this paper they are analyzed in millimeter wave regimes. The study focuses on the key limiting factors and in particular the optimum number of transistors from which the key performance parameters such as maximum possible operating frequency, output power, and efficiency are achieved. Based on the analysis, design trade-offs of stacked MOS PAs are presented. The frequency dependency of the optimum load presented to each stack is analyzed to express the overall performance of the mentioned PA topologies as a new optimization method. Additionally, it is shown how the optimal load variations translate into amplitude-to-amplitude/phase (AM-AM/PM) conversion distortions. The validity of the analysis is examined against simulations. The simulations are performed based on 8M1P CMOS 28nm technology and electromagnetic simulations in ADS Momentum.

This paper concerns with the nonlinearity analysis and compensation of active phase shifters based on vector modulator topologies which utilize Gilbert cell type multipliers. In this respect, both frequency dependence and expansion behavior of such topologies are analyzed. Based on translinear circuits theory, log/anti-log nonlinear equations are transformed to algebraic linear equations and/or multiplication equations, which facilitates solution for such nonlinear equations. To validate the analyses, a 5-bit active phase shifter was designed and simulated in 0.13um HBT technology node. 3D electromagnetic simulation results verify the consistency of the analysis and proposed compensation technique.

At sub-THz frequencies, the local oscillation for transceivers is often generated by an analog frequency multiplier tree. This paper studies the origins and minimization of spurious tones in a local oscillator multiplier consisting of a chain of frequency doublers. It is found that the nearest spurious components depend on the leakage of the input signal in the first multiplier, which can be minimized by active bias tuning, filtering in the first stage or better balance in the driving differential signal. To verify the nonlinearity modeling, 0.13-μm SiGe BiCMOS technology has been utilized.

This paper proposes how to define the optimum number of stacked transistors in a multi-stacked CMOS power amplifier (PA) topology, based on several physical as well as circuit design aspects. Starting with a systematic concept, the analysis then goes through the relevance of transistor transconductance, aspect ratio, parasitics, operating frequency, and the number of transistor stages in a pentagonal trade-off concept. While this is done based on theoretical circuit analysis, the results, then, are evaluated using simulations based on 45nm CMOS technology.

This paper shows how digital predistortion of a phased array can benefit from the parametric variations over parallel power amplifiers (PAs). Different antenna configurations are simulated by varying the PA input drive levels by the Monte-Carlo method. The error vector magnitude (EVM) at the steering angle and total radiated adjacent channel power ratio (TRACPR) are used as performance metrics. The simulation results indicate that array predistortion can benefit from the variations between the PAs to improve the EVM significantly. However, at the same time, the TRACPR performance is reduced. This gives a new trade-off to balance between in-band and out-off-band distortion in the fifth generation beamforming systems.

There is a limited amount of scavenging alternatives for smartphones. We assess the feasibility of using indoor light to extend smartphones' battery life. We build a prototype charger that demonstrates that indoor light scavenging is a practical method that can substantially extend battery life on smartphones. The results show that it is feasible and practical to extend battery life with this energy harvesting method. We finally discuss certain obstacles that need to be overcome, especially the redesign of operating systems to account for energy harvesting.

A prototype analog correlator structure suitable for a WCDMA-receiver was implemented. The advantages of this correlator are low power consumption (compared to a digital correlator) and small chip area. The target is to use such correlators as parallel correlators (fingers) of a RAKE receiver. The analog baseband correlator utilizes passive MOS-multipliers, a first-order low-pass continuous-time oversampling sigma-delta analog-to-digital converter and a second order sine type of decimation filter (for both I and Q input paths). The modulator sampling rate is twice the chip rate with oversampling ratios of 8 to 512 depending on the PN code length. The circuit was implemented in 0.8 /spl mu/m CMOS-technology with a supply voltage of 2.8 V. The layout size is 345 /spl mu/m/spl times/686 /spl mu/m and the current drain is approximately 370 /spl mu/A.

Source impedance Zs plays an important role by minimizing the distortion of a common-emitter BJT-stage. Care has to be taken to achieve the proper impedance not only at the fundamental, but also at the frequencies of the 2nd-order signal. Volterra analysis is applied in order to gain an insight into distortion mechanisms. By providing the optimum Zs at different frequencies, significant improvement in linearity can be achieved.

CMOS time-to-digital and digital-to-time converters (TDCs and DTCs) with sub-ns accuracy are used in receiving and generating angle modulated signals, resulting in fully integrated, low power digital implementations. The TDC used in a digital FM demodulator circuit and the DTC used in a high-precision interpolating frequency synthesizer are presented with measured results.>

A time measurement circuit based on the principle of the multiple-phase oscillator is presented. The multiple phases are realized with a delay line ring oscillator, resulting in a compact, simple structure. The circuit is implemented in 5 V, 1.2 um CMOS process. The measured single-shot resolution is 1.5 ns (sigma-value) and the maximum measured error is 4 ns in the measurement range 5 ns -10 us with temperature variation between -40 to +60/spl deg/C and supply voltage variation between 4.5 and 5.5 V. Nominal current consumption is 2.5 mA.>