Hamid Reza Naji

dblp:79/5995 · DBLP profile ↗
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9ranked-venue papers
4as first author
3since 2021 · last 2025
0000-0001-8422-2433ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 6 · 3 first-author · 3 since 2021Artificial intelligence and machine learning · 2Security and privacy · 1 · 1 first-author
YearPublicationVenuePosition
2025 Reduction of energy consumption in cloud data centers with proper placement of virtual machines
Hamid Reza Naji, Reza Esmaeili
J. Supercomput.1
2024 An efficient resource allocation of IoT requests in hybrid fog-cloud environment
Mahboubeh Afzali, Amin Mohammad Vali Samani, Hamid Reza Naji
J. Supercomput.3
2024 Parallel design of SFO optimization algorithm based on FPGA
Hamid Reza Naji, Soodeh Shadravan, Hossien Mousa Jafarabadi, Hossien Momeni
J. Supercomput.1
2020 A Fault-Tolerant Workflow Scheduling Algorithm for Grid with Near-Optimal Redundancy
Alemeh Matani, Hamid Reza Naji, Hassan Motallebi
J. Grid Comput.2
2019 The Sailfish Optimizer: A novel nature-inspired metaheuristic algorithm for solving constrained engineering optimization problems
Soodeh Shadravan, Hamid Reza Naji, Vahid Khatibi Bardsiri
Eng. Appl. Artif. Intell.2
2017 A Clustering Algorithm for Communication-Aware Scheduling of Task Graphs on Multi-Core Reconfigurable Systems
abstract
In this paper, a clustering algorithm called the Reconfigurable Dominant Sequence Clustering (ReDSC), is proposed. The experiments show that ReDSC reduces the parallel run time efficiently by 30 percent. Moreover, an empirical comparison of ReDSC with its peer in the multi-processor model, i.e., DSC algorithm, is provided and the results demonstrate the 35 percent improvement of ReDSC over DSC. Then, a hardware implementation of a dynamic scheduler for run-time communication-aware scheduling of hardware tasks is proposed. The proposed scheduler makes use of the ReDSC algorithm for allocating tasks to the processing reconfigurable cores, dynamically considering the communication costs. The simulation results illustrate the benefits of the proposed scheduler as compared to that of other static and basic schedulers in the technical literature.
Amin Yoosefi, Hamid Reza Naji
IEEE Trans. Parallel Distributed Syst.2
2016 Parallel Massive Data Monitoring and Processing Using Sensor Networks
abstract
Sensor Networks have great potential for many applications. In time-critical and security applications, it is important to have on time delivery, minimum access time and maximum data rate. Most of sensor networks have a large number of sensor nodes which considering the memory and processor of each of them all together they provide a huge data storage space and also high processing capability. In this paper we propose a method to implement the parallel data monitoring and processing on a large number of sensor nodes in a sensor network that can be used is a security environment. We can use the sensor, memory and processing elements of each sensor node store and process a part of large database or computation. The data which is entered to the database can come from the sensors of sensor nodes. By this method not only we can use the memory of each sensor node to store apart of our data but also we can do parallel processing on the stored data of all sensor nodes. The results of our simulations show this method provides a huge storage space to store a considerable amount of data and also speed up the computations.
Hamid Reza Naji, Najmeh Rezaee
ISI1
2014 An efficient crossover architecture for hardware parallel implementation of genetic algorithm
Rasoul Faraji, Hamid Reza Naji
Neurocomputing2
2004 Creating an adaptive embedded system by applying multi-agent techniques to reconfigurable hardware
Hamid Reza Naji, B. Earl Wells, Letha H. Etzkorn
Future Gener. Comput. Syst.1