Multi-Processor Systems-on-Chip (MPSoC) can deliver high performance needed in many industrial domains, including aerospace. However, their high power consumption , combined with avionics safety standards , brings new thermal management challenges. This paper investigates techniques for offline thermal-aware allocation of periodic tasks on heterogeneous MPSoCs running at a fixed clock frequency, as required in avionics. The goal is to find the assignment of tasks to (i) cores and (ii) temporal isolation windows, as required in ARINC 653 standard, while minimizing the MPSoC temperature. To achieve that, we formulate a new optimization problem , we derive its NP-hardness, and we identify its subproblem solvable in polynomial time . Furthermore, we propose and analyze three power models, and integrate them within several novel optimization approaches based on heuristics, a black-box optimizer, and Integer Linear Programming (ILP). We perform the experimental evaluation on three popular MPSoC platforms (NXP i.MX8QM MEK, NXP i.MX8QM Ixora, NVIDIA TX2) and observe a difference of up to 5.5 °C among the tested methods (corresponding to a 22% reduction w.r.t. the ambient temperature). We also show that our method, integrating the empirical power model with the ILP, outperforms the other methods on all tested platforms.

This paper provides an overview of the ongoing work to enable novel modalities of passive monocular neuromorphic vision in the NimbleAI sensing-processing architecture; namely, foveated and light-field event-driven vision with selective visual attention. The latter vision modality encodes 3D visual surroundings as sparse visual events in a 4D spatiotemporal domain, adding depth to current representation of visual information delivered by Dynamic Vision Sensors (DVS). The NimbleAI architecture implements hardware support for efficient execution of mainstream computer vision algorithms and AI models using these visual inputs. The architecture is designed to harness the latest advancements in 3D silicon integration, making it possible to squeeze sensing and spiking circuitry, memory, and processing engines into a miniature silicon volume.

The NimbleAI Horizon Europe project leverages key principles of energy-efficient visual sensing and processing in biological eyes and brains, and harnesses the latest advances in$\mathbf{33D}$stacked silicon integration, to create an integral sensing-processing neuromorphic architecture that efficiently and accurately runs computer vision algorithms in area-constrained endpoint chips. The rationale behind the NimbleAI architecture is: sense data only with high information value and discard data as soon as they are found not to be useful for the application (in a given context). The NimbleAI sensing-processing architecture is to be specialized after-deployment by tunning system-level trade-offs for each particular computer vision algorithm and deployment environment. The objectives of NimbleAI are: (1)$\mathbf{100x}$performance per mW gains compared to state-of-the-practice solutions (i.e., CPU/GPUs processing frame-based video); (2)$\mathbf{50x}$processing latency reduction compared to CPU/GPUs; (3) energy consumption in the order of tens of mWs; and (4) silicon area of approx. 50 mm2.

In the safety-critical domain, such as avionics, there is a strong demand for increased guaranteed performance and lower development costs. This demand is satisfied by utilizing commercial off-the-shelf (COTS) Multiprocessor System-on-Chips (MPSoC). MPSoCs contain multi-core processors that pose a significant challenge for deployment in safety-critical systems, since the Worst-Case Execution Time (WCET) of a process may be influenced by other processes due to cross-core interference.In this paper, we introduce a novel non-intrusive IP Core for Cache and Memory Thrashing (referred to as IP-CMT) that helps us estimate the cross-core interference. The IP-CMT core does not require any software changes to be made to the system under test, resulting in lower development costs. Furthermore, our evaluation with a real-world aerospace-grade Flight Management System indicates that the proposed IP-CMT core is capable of introducing the same degree of cross-core interference as present-day SW methods while not being overly conservative and having minimal overhead. Thus, system performance is spared.

The demand for high-performance computing leads to the adoption of modern Multi-Processor System-on-Chip platforms in the avionics domain, where many applications are safety-critical. To fulfill the safety requirements, it is vital to avoid the platform’s overheating. In this paper, we propose a task mapping method, MultiPAWS, for thermal-aware allocation of the safety-critical avionics workloads under time isolation constraints. With the help of MultiPAWS, we jointly find an optimal number of scheduling windows and their lengths and optimal mapping of the workload to these windows and available CPU cores. To guide the optimization, we introduce a thermal model based on power-characteristic coefficients, which we experimentally identify for a benchmark dataset on NXP i.MX8QuadMax platform (based on ARMv8 big.LITTLE architecture). Furthermore, to mimic the execution of safety-critical avionics applications, we introduce DEmOS, an open-source Linux-based scheduler. DEmOS provides a time-partitioned scheduling similar to the ARINC 653 standard. We use DEmOS for the experimental evaluation on the i.MX8 platform. The experimental results suggest that MultiPAWS achieves over a 12% decrease of the platform temperature compared to the minimum-utilization-based approach. Moreover, we demonstrate how MultiPAWS can be used in design space exploration for finding the tradeoff between the platform temperature and the length of the scheduling hyper-period.

Full-system emulators allow the execution of guest operating systems and applications without the need of having access to the real target hardware. For many applications, besides the correct functional modeling, the full-system emulator shall also be time-accurate. In this paper, we present a new full-system multi-core simulator that delivers time-accurate execution and preserves the functional correctness of guest application. The proposed solution is based on QEMU. We enriched QEMU with various time models of multi-core platforms. We call this new full-system simulator mcQEMU. mcQEMU supports guest CPUs with out-of-order and in-order architectures.We validated mcQEMU by emulating multi-core ARM processors in system mode. The time accuracy of mcQEMU is evaluated with the TACLeBench benchmark suite. From a timing prediction viewpoint, mcQEMU achieves an estimation error of only 15% in average when emulating the out-of-order i.MX6Quad processor by NXP. For full-system simulation, mcQEMU runs at 35 Mips for in-order architectures and 25 Mips for out-of-order ones. In user-mode simulation, mcQEMU can achieve up to 65 Mips.

Many modern computing platforms in the safety-critical domains are based on heterogeneous Multiprocessor System-on-Chip (MPSoC). Such computing platforms are expected to guarantee high-performance within a strict thermal envelope. This paper introduces a testbed for thermal and performance analysis. The testbed allows the users to develop advanced scheduling and resource allocation techniques aiming at finding an optimal trade-off between the peak temperature and the achieved performance. This paper presents a new, open-source Thermobench tool for data collection and analysis of user-defined workloads. Furthermore, a methodology for shortening the time needed for the data collection is proposed. Experiments show that a significant amount of time can be saved. Specifically, time reduction from 60 minutes to 15 minutes is achieved with the i.MX8 MPSoC from NXP while running a set of user-defined benchmarks that stress CPU, GPU, and different levels of the memory hierarchy.