This paper shows a FeFET-based analog multi-level unit cell for computing-in-memory applications for Deep Neural Networks (DNN). The FeFET-based unit cell performs input-weight multiplication with a Back-End-Of-Line (BEOL) ferro-electric HZO FeFET device on top of standard 180 nm CMOS circuits. The unit cell works with a feedback mechanism which combines an in-house FeFET device to store weights and CMOS transistors underneath to provide outputs in current mode to be integrated over time on a capacitor. Said feedback mechanism compensates for device-to-device variability, and would permit to calibrate a system against time variations, something not usually included in cross-bar solutions. Joint electrical simulations of the FeFET-CMOS circuit are performed with a compact Verilog-A model extracted from the experimental characterization of the FeFET devices. Electrical simulations show that our feedback approach leads to a multi-bit cell with 5-bits of resolution, superior to that of state-of-the-art solutions.

This live demonstration shows a mixed-signal design in 180 nm CMOS technology that runs hyperdimensional computing (HDC) on binary hypervectors with up to 8,192 components. The chip comprises 64 × 128 processing elements (PE) arranged in a 2D mesh with direct connection to their first neighbors. PEs include a 1-bit ALU with a 16 6T-SRAM bank to execute HDC primitives. Hypervector classification is performed through the Hamming distance with current sources in every PE globally connected to an analog computing unit laid down outside the PE array. The overall approach results in tens of nJ of power consumption in inference, which is competitive with state-of-the-art solutions.

This live demonstration shows a mixed-signal Computer In Memory (CIM) macro deep neural network (DNN) integrated circuit in 180 nm CMOS technology for image recognition. Images are coded as pulse width modulation (PWM) signals. DNN weights are stored as voltages in 6T-SRAM memories which drive current sources inside every multiplier. Multipliers are arranged within processing elements laid down in a 2D mesh suitable for image processing. The power consumption per multiplier of the CIM macro is of 0.22 µW, below state-of-the-art competitors following the same multiply and accumulate (MAC) principle.

Neural network mixed-mode hardware accelerators for deep convolutional neural networks (CNN) strive to cope with a high number of input feature maps and increasing bit depths for both weights and inputs. As an example of this need, the ResNet model for image classification comprises 512 3× 3 feature filters in its conv5 layer. This would lead to 4068 multipliers driving a summing node for actual concurrent processing of all the input feature maps, which makes up a challenge in mixed-mode. This paper addresses the design of a 5-bit signed SRAM-based in-memory computing cell in 180 nm 3.3 V CMOS technology, dealing with the impact of increasing the number of input feature maps. The data presented in the paper are based on electrical and post layout simulations.

Background subtraction is one of the first steps in many video processing algorithms. Thus, a real-time processing with low power consumption is convenient for different applications where power hungry devices with high computational capabilities can not be deployed. This work presents the design of a 24×56 pixel proof-of-concept 0.18 μm standard CMOS vision sensor chip implementing the foreground detection algorithm Hardware Oriented Pixel Based Adaptive Segmenter (HO-PBAS) on the focal plane. Simulation results show a maximum processing speed of 2000 fps with a figure of merit of 1.3 μW/pixel at 60 fps and a pixel pitch of 47 μm in a four pixels per processing element configuration.

An ultra-low power LDO regulator with an adaptive biasing error amplifier is presented in this paper. An absolute difference voltage meter circuit section based on super source followers is used to achieve the adaptive biasing scheme. The experimental total quiescent current consumption is as low as 1.88 nA with a measured line sensitivity of 0.13 mV/V in a circuit occupying 1473 μm2of silicon area.

This paper presents a 1 mm2solar cell and a Power Management Unit (PMU) on the same substrate to rise up the harvested voltage above 1.1 V to power wearable or implantable devices. The on-chip solar cell and the PMU are fabricated in standard 0.18 μm CMOS technology achieving a form factor of 1.575 mm2. Experimental results show that the PMU is able to start-up from a harvested power of 2.38 nW without any external kick off or control signal and can handle a harvested power up to μW with a continuous and two-dimensional Maximum Power Point Tracking (MPPT) that works in open-loop mode to set the frequency, the gain and the capacitor sizes of a charge pump.

This paper presents an indirect Time-of-Flight sensor for standard CMOS technologies with an alternative demodulation scheme based on homodyne techniques. This avoids control signals shorter than the period of the emitted light signal, which prevents synchronization issues and minimizes switching effects like charge injection and clock feedthrough. The feasibility of the pixel and the demodulation scheme is demonstrated through simulations.

This live demonstration is related to ISCAS track “4.5: Circuits & Systems for Energy Harvesting”. This live demo shows a micro-energy harvesting system which includes a 1 mm2solar cell as the unique power source and a Power Management Unit (PMU) on the same substrate in standard 0.18 μm CMOS technology. The PMU has cold start-up from nW and it also performs a continuous and two-dimensional maximum power point tracking using analog strategies to meet very low power consumption, managing a high input power range. The system is used to power an off-chip NAND gate.

Foreground segmentation algorithms are sometimes provided with feedback mechanisms to deal with complex scenarios such as dynamic backgrounds. This is accomplished with background dynamic estimators in the case of foreground detectors based on non-parametric models with a historical record of the background. This work introduces the Shannon entropy as a new background dynamics estimator. The paper shows that this approach leads to better figures of merit than those provided by the original background dynamics estimators in state-of-the-art algorithms such as PBAS and SuBSENSE for complex scenarios as dynamic backgrounds or camera jitter in the database ChangeDetection. Also, the Shannon entropy permits to decrease the number of samples in the background model, cutting memory usage, and thus making implementations on embedded devices easier.

The high number of memory accesses in background subtraction algorithms constraints the choice of the memory topology of an analog implementation of a hardware-oriented version of the well-known PBAS algorithm (HO-PBAS). As the first step towards the implementation of a CMOS vision chip with per-pixel processing to run the HO-PBAS, this work assesses the impact of the circuit non-idealities of the three main analog memory topologies into the segmentation result on the CDNET database.

This paper presents a dynamic model for on-chip inverting capacitive charge pumps driven by two non-overlapping clock signals. The model implements the charge reusing technique to mitigate the efficiency loss due to the charge and discharge process of the parasitic capacitances. Validation with both circuit-level simulations and experimental results is shown, demonstrating high accuracy. An application example in micro energy harvesting is given.

This live demonstration is related to ISCAS track “Sensory Systems: Sensor Networks”. This live demo shows a wireless sensor network of custom-made differential capacitive sensors with the ZigBee protocol for snail pest detection. The wireless sensor network provides the snail occupation level of a given plantation area. Validation of the wireless sensor network in both controlled mini plots in a greenhouse and outdoor small areas has been made.

This paper introduces a Time-of-Flight sensor of 50 × 60 pixels in standard CMOS 0.18 μm technology with in-pixel adaptive number of accumulations and background suppression. Background suppression is carried out through two mechanisms, namely, the increase of signal to background ratio, and background subtraction. The pixel features a fill factor of 77% with an nwell over p-substrate diode of 50 × 50 μm2. The pixel senses the photocurrent through a transimpedance amplifier. Adaptive accumulations are performed with an in-pixel comparator that is also used for per-column A/D conversion as part of an 8-bit single-slope ADC. The sensor works with 4 square pulses of 50 ns. Simulations show that the chip could measure distances up to 7.5 m without optical filters for background levels up to 20 klux at video frame rate.

This paper studies the dark current (DC) of the photodiode (PD), the transmission gate (TG), and the floating diffusion (FD) in 4-Transistor (4T) pixels in standard CMOS technologies for Time-of-Flight (ToF) sensors through device simulations. The paper addresses the layout optimization in terms of DC for an nwell/psub and two custom pinned-photodiodes (PPD), stating their pros and cons.

This live demonstration is related to ISCAS track “Imagers and Vision Processing”. It showcases the Gaussian pyramid with a CMOS vision sensor with a 176 × 120 pixel array in standard 0.18 μm CMOS technology. The sensing elements are 3T-APS with in-pixel ADC and CDS. The Gaussian pyramid is extracted concurrently with a double-Euler switched-capacitor network on the same substrate, giving RMSE errors below 1.2% of FSO. The chip provides a Gaussian pyramid of 3 octaves with 6 scales each with an energy cost of 26.5 nJ/px at 2.64 Mpx/s.

This paper proposes a hardware implementation to speed up the calculation of the feature descriptor vector in the Scale-Invariant Feature Transform (SIFT) algorithm. The proposed architecture, which improves conventional solutions based on embedded processors or other hardware/software co-designs, computes a feature descriptor vector of 27 elements from a keypoint neighborhood of 15×15 pixels. This process comprises several steps, including complex operations such as vector normalization operations. The paper compares two different implementations: one being time-optimized and the other memory-optimized. Both approaches require 649 and 874 clock cycles respectively for a single feature vector calculation (6.49 μs and 8.74 μs for a 100 MHz FPGA).

This paper assesses the implementation of scale-and rotation-invariant feature detectors on Cellular Processor Arrays (CPA). Scale- and rotation-invariant feature detectors are complex image processing algorithms with a high computational burden in the low-level image processing stage due to large-neighborhood convolution-type operations. Such operations are used to generate the so-called scale-space. This paper outlines different options to provide the scale space in the Scale Invariant Feature Transform (SIFT) and the Speeded-Up Robust Features (SURF) algorithms on CPAs with pixel-per-processor assignment. The paper shows that it is feasible to do this even with a reduced set of inter-processor communications within acceptable time limits on existing CPAs.

This paper introduces an architecture of a switched-capacitor network for Gaussian pyramid generation. Gaussian pyramids are used in modern scale- and rotation-invariant feature detectors or in visual attention. Our switched-capacitor architecture is conceived within the framework of a CMOS-3D-based vision system. As such, it is also used during the acquisition phase to perform analog storage and Correlated Double Sampling (CDS). The paper addresses mismatch, and switching errors like feedthrough and charge injection. The paper also gives an estimate of the area occupied by each pixel on the 130nm CMOS-3D technology by Tezzaron. The validity of our proposal is assessed through object detection in a scale- and rotation-invariant feature detector.

Modelling of physical phenomena often involves the use of complex systems of equations whose computational solution has demanding requirements in terms of memory and computing power. Among the different techniques proposed, the Finite-Difference Time-Domain (FD-TD) method has the advantage of a feasible hardware implementation that can significantly speed up the computations. This technique is widely used for the solution of partial differential equations in a variety of areas such as antennas design, medical studies, circuit packaging and non-destructive evaluation. In this paper, we present a hardware accelerator of a 3D FD-TD heat equation solver that constitutes the basis of a thermal model of the soil for the non-destructive evaluation of minefields using infrared thermography techniques. In order to be able to work on the field during mine removal activities, a portable and computationally efficient system must be achieved. To this aim, we projected the 3D FD-TD model of the soil onto an FPGA platform using Handel-C and VHDL. A speedup factor of 34 over a single precision PC (C++) is achieved.

In this paper a new technique for segmenting and tracking moving objects in a user-defined control area is presented. It is based on an active contours technique called Pixel-Level Snakes (PLS) whose capabilities to manage changes of contour topology and to introduce additional constraints in the contour evolution are used to define a control area as well as to segment and track moving objects. Furthermore, PLS can reach a very high speed of response when they are implemented on a pixel-parallel hardware platform. To illustrate the validity of the proposal some examples and results regarding the computation time achieved in the implementation of the proposed algorithm on a cellular processor array (SCAMP-3 vision chip) have been included.

Modeling of physical phenomena often involves the use of complex sets of equations whose computational solution has demanding requirements in terms of memory and computing power. Finite-Difference Time-Domain (FD-TD) method is a technique widely used nowadays in a variety of areas, such as antennas design, medical studies, circuit packaging and non destructive evaluation (NDE), having the advantage of a feasible hardware implementation of the algorithm that can significantly speedup the computations. In this paper we will focus on the thermal modeling of the soil for NDE. To this aim we projected a true 3D FD-TD model of the soil on an FPGA. Two different implementations of the system were made, one developed with VHDL and another one with Handel-C. A speed-up factor of 160 over a PC is achieved which shows the utility of such an implementation.

The use of a reduced set of multipliers or coefficient circuits on cellular processor arrays leads to time and area efficient solutions. The reduced set of multipliers is achievable with the so-called split&shift (S&S) methodology. Data resultant from applying such a methodology to implementations with cellular non-linear networks (CNN) reported in the literature are presented. Also, pixel-level snakes (PLS) are used as benchmark for a more in-depth analysis of our methodology.

Electronic speckle pattern interferometry (ESPI) is a well-known technique in the realm of optoelectronics by which a fringe pattern is formed when two coherent light beams (typically lasers) interfere after, at least one of them, is reflected off a rough surface. The resultant image is acquired by electronic means, with either a CCD camera or CMOS imagers. Observation of the fringe pattern gives information about a measurement. Examples of such measurements are displacement of an object, surface deformation, vibration, velocity, etc. Image analysis is required to read and interpret the underlying information conveyed in the fringe pattern. This paper merges ESPI with cellular non-linear networks (CNN). The final goal is to run ESPI image processing on CMOS CNN-based chips to cover applications with hard time requirements. The current work addresses the first stage which is noise removal through spin filters with CNN operators.

Infrared thermography is a technique for the detection of plastic mines. Its application requires the solution of the equations that govern the heat transfer processes. We present an FPGA projection of a system that solves these equations

The use of infrared (IR) images of the soil is an efficient technique to detect shallowly buried landmines. The detection is possible due to the different thermal properties of the soil and the mine. The core of this technique is the simulation of the heat transfer processes in the soil and at the soil-air interface. Simulation of these processes is a very long-time consuming task on ordinary computers. Its execution on dedicated hardware can reduce the computing time. In this paper we show the architecture of a system that simulates the thermal processes onto an FPGA, showing the feasibility of such a realization.

In this paper, we address the problem of the detection and identification of surface-laid and shallowly buried landmines from measured infrared images. A three-dimensional thermal model has been developed to study the effect of the presence of landmines in the thermal signature of the bare soil. Based on this model, a target identification procedure is proposed aiming at detecting and classifying the anomalies found on the soil thermal signature. In our approach, landmines are thought of as a thermal barrier in the natural flow of the heat inside the soil, which produces a perturbation of the expected thermal pattern on the surface. The detection of these perturbations will put into evidence the presence of potential mine targets. We propose an iterative procedure to classify the detected perturbations as mines or nonmines and to estimate their depth of burial. This paper describes the main principles of our method and illustrates classification results on a set of acquired images. Qualitative and quantitative comparisons with independent component analysis are also given.

An alternative to classical image segmentation based on active contour techniques is discussed. The approach is based on deformable contours which evolve until reaching a final desired location. The contour shift is guided by external information from the image under consideration which attracts them towards the target characteristics (intensity, extremes, edges,...) and by internal forces which try to maintain the smoothness of the contour curve. These forces act on each pixel of the contours, resulting in a high degree of freedom for the contour evolution and provide a high flexibility for the evolution dynamics of the snakes which allows the solution of complex tasks as is the case for topologic transformations. This, along with the use of only local information will allow the algorithm implementation into an array of processors leading towards "pixel-level" contour processing.

Genetic algorithms are applied to design multilayer discrete-time cellular neural networks for image processing tasks, To this end not only the templates of the different layers will be optimized, but also the network structure itself, that is, number of layers and iterations per layer. As a difference with traditional strategies, both the definition of the optimum network size and the template optimization are done simultaneously.

Detection and clearance of buried mines is a big problem with lots of humanitarian, environmental and economic implications. Classic techniques, such as metal detectors, are not suitable for detecting mines with low or null metal content. In this work we propose a novel method based on the analysis of the different thermodynamic behaviour of the mines and the soil using a sequence of infrared images. In order to process this information, we propose the use of a specific type of neural network characterized by its parallel nature, high processing speed, low cost and power consumption and small size.

Perceptual organisation can be defined as the ability to impose structural organisation on sensory data, so as to group sensory primitives arising from a common underlying cause. Our organisational philosophy is hierarchical, with complex organisations being formed from simpler ones. In this paper, directional features extracted from Gabor responses are used as the primitives for perceptual grouping. In previous work, we extracted Gabor features in 8 directions and then applied two SOMs, thus classifying each pixel in the image within a 8x10 neuronmap, each corner of which represents one of four main directions, (horizontal, vertical, left diagonal and right diagonal). In the present work we group pixels with similar directional features, thereby detecting salient structures within an image.

In this work, we have developed a computer-aided diagnosis system, based on a two-level artificial neural network (ANN) architecture. This was trained, tested, and evaluated specifically on the problem of detecting lung cancer nodules found on digitized chest radiographs. The first ANN performs the detection of suspicious regions in a low-resolution image. The input to the second ANN are the curvature peaks computed for all pixels in each suspicious region. This comes from the fact that small tumors possess and identifiable signature in curvature-peak feature space, where curvature is the local curvature of the image data when viewed as a relief map. The output of this network is thresholded at a chosen level of significance to give a positive detection. Tests are performed using 60 radiographs taken from routine clinic with 90 real nodules and 288 simulated nodules. We employed free-response receiver operating characteristics method with the mean number of false positives (FP's) and the sensitivity as performance indexes to evaluate all the simulation results. The combination of the two networks provide results of 89%-96% sensitivity and 5-7 FP's/image, depending on the size of the nodules.

The main objective of this work is to design an approach for the study of textures that is capable of handling textures of different sizes in the same resolution scale. In addition, we want this approach to be independent from the images it analyzes in order to make it valid for the largest possible number of application fields. These considerations have led us to using a Markov random field model in which we have modified its probabilistic dependence so that it is capable of analyzing microtextures and macrotextures simultaneously. These modifications are carried out by means of the introduction of a new non-standard system of neighbors, called functional neighbors. Finally, we show how Markov's random field with a system of functional neighbors provides better results in texture classification tasks than with a system of physical neighbors.