A time-domain stochastic flash ADC was fabricated using a 12-nm FinFET technology. Its analog input in the voltage domain is transformed into time-domain pulses, which are then sent to a time-to-digital converter (TDC) comprising 405 time comparators. To distinguish the signal timing amplitude, the random input-referred offsets of these comparators are utilized. An input distribution network is employed to broaden the input range of the TDC. A code-mapping calibration method is used to improve the conversion linearity and mitigate the effects of variations in process, voltage, and temperature. Operating at a 12-GS/s sampling rate, the ADC chip consumes 110.7 mW from a 0.8 V supply. It occupies an active area of$480\times 125~\mu \text {m}^{2}$. The ADC achieves an SNDR better than 40.5 dB and an SFDR better than 50.7 dB for input frequencies up to 5.8 GHz.

Due to its excellent power efficiency, the successive-approximation-register (SAR) analog-to-digital converter (ADC) is an attractive design choice for low-power ADC implements. In analog layout design, the parasitics induced by interconnecting wires and elements affect the accuracy and performance of the device. Due to the requirement of low-power and high-speed, series of very small lateral metal-metal capacitor units are usually adopted as the architecture of capacitor array. Besides power consumption and area reduction, the parasitic capacitance would significantly affect the matching properties and settling time of capacitors. This work presents a framework to synthesize good-quality binary-weighted capacitors for custom SAR ADC. Also, this work proposes a parasitic-aware ILP-based weight-dynamic network routing algorithm to generate a layout considering parasitic capacitance and capacitance ratio mismatch simultaneously. The experimental result shows that the effective number of bits (ENOB) of the layout generated by our approach is comparable to or better than that of manual design and other automated works, closing the gap between pre-sim and post-sim results.

For an ADC that periodically converts a time-varying analog input, the jitter in the ADC's sampling clock introduces sampling errors, degrading the ADC's dynamic performance. This paper describes a jitter compensation technique to mitigate the effect of sampling clock jitters. Clock jitter is detected by using an extra ADC that samples a reference clock. Sampling errors are then canceled by using a digital differentiator with the acquired jitter estimates. Experiment on a test chip shows that this technique improves the SNR performance of a 12-bit 247-MS/s ADC from 51.9 dB to 56.3 dB when the input is an$\boldsymbol{80}-\mathbf{MHz} -1-\mathbf{dBPS}$sinewave. A sampling clock with 4.89 ps rms jitter drives the ADC.

We describe a technique that digitally converts a pulse-code-modulated (PCM) signal to a pulse-width-modulation (PWM) signal. This technique is based on the naturally sampled PWM emulation scheme. Its computation is simplified by using empirical models. It provides sufficient accuracy with minimal computation. At 384 kHz sampling rate, the proposed technique can convert a sine wave to a PWM signal and achieve better than -92 dB total harmonic distortion (THD) for a sine wave frequency up to 20 kHz and a sine wave amplitude up to 90% of the full range.

This paper presents a digital-subranging (sub-R) analog-to-digital conversion (ADC) architecture to improve the operation speed of sub-R ADCs. Long latency between coarse and fine conversions will slow down the conventional sub-R ADCs. The proposed digital-sub-R uses digital circuits to implement the sub-R function and shorten this latency, thus benefits the CMOS scaling. Furthermore, the dynamic comparators are used to save more ADC power consumption. Their accuracy is improved by the proposed pseudodifferential offset calibration loop. The digital-sub-R also helps to reduce the dynamic offset of the fine comparators caused by the input common-mode variation. Fabricated using a 55-nm CMOS technology, the reported 8-bit 1-GS/s ADC consumes only 16 mW from a 1.2 V supply. Measured signal-to-noise ratio (SNR) and spurious free dynamic range (SFDR) are 46 and 55 dB, respectively. Measured effective number of bits (ENOB) is seven bits at 10-MHz input frequency. At Nyquist input, the ENOB performance of 6.3 bits is still maintained. Its figure-of-merit is 197-fJ/conversion-step.

A 2-1 MASH delta-sigma modulator (DSM) was fabricated using a 90nm CMOS technology. Operating at 6.25 MHz clock rate, this chip consumes 860 μW under a 1 V supply. The over-sampling ratio is 128, and the signal-bandwidth is 24.4 kHz. This chip achieves a performance of 88 dB SNDR and 90 dB SNR. Its dynamic range is 100 dB. The chip area is 0.44 mm2.

A 10-bit 200-MS/s pipelined ADC was fabricated using a 90 nm CMOS technology. Switching opamps are used to save power. They are designed for high speed and fast turn-on time. Digital background calibration is used to correct the conversion error caused by the low dc gain of the opamps. The ADC consumes 26 mW from a 1.1 V supply. Its measured DNL and INL are +0.98/−0.81 LSB and +1.4/−1.5 LSB respectively. Its measured SNDR and SFDR are 55 dB and 67.2 dB respectively. The chip active area is 0.69 mm2.