The explosive growth in cloud-computing and overall data center system growth has created an unprecedented demand on system architects and designers to continuously develop more complex system networks to effectively satisfy the insatiable appetite to process, move, and store large amounts of data. Nonlinear system behavior caused by emerging workloads and use-cases, varying end-to-end congestion protocols, and heterogeneity in the various compute and storage capabilities of custom designed accelerators further compounds the design problem. Modern simulation methodologies lack a cohesive and efficient framework to address the interoperability of the intersecting layers at scale. In this paper, we present a simulation framework for evaluating congestion control protocols. Furthermore, we present a set of optimizations that enable analysis for longer simulated times and at network scales up to 128K nodes, which is vital for proper analysis of workloads that require long run times (e.g., AI training) or workloads that are known to have scaling issues (e.g., RDMA). Specifically, we evaluate congestion control performance at various scales, study the implications of topology scaling on congestion, and the performance impact of simultaneous heterogeneous protocols.

10 GbE connectivity is expected to be a standard feature of server platforms in the near future. Among the numerous methods and features proposed to improve network performance of such platforms is direct cache access (DCA) to route incoming I/O to CPU caches directly. While this feature has been shown to be promising, there can be significant challenges when dealing with high rates of traffic in a multiprocessor and multi-core environment. In this paper, we focus on two practical considerations with DCA. In the first case, we show that the performance benefit from DCA can be limited when network traffic processing rate cannot match the I/O rate. In the second case, we show that affinitizing both stack and application contexts to cores that share a cache is critical. With proper distribution and affinity, we show that a standard Linux network stack runs 32% faster for 2 KB to 64 KB I/O sizes.

Since the introduction of the 10 GbE standard in 2002, the ability of general purpose processors to efficiently process network traffic with common protocols such as TCP/IP has been revisited and critically evaluated. However, recent commercially available processors such as IntelregCoretrade 2 Duo Processor introduce microarchitectural enhancements that could significantly influence the approach to accelerating network processing. We examine the network performance of a real platform containing IntelregCoretrade micro-architecture based processors, the role of coherency and a prototype implementation of direct cache placement (direct cache access or DCA) of inbound network traffic. We observe that a substantial portion of the time relates to the inefficiency of I/O specific coherence protocols in the platform. We demonstrate that a relatively, low complexity implementation of DCA called 'Prefetch Hint' provides a 15 to 43% speed-up to receive-side processing across a range of I/O sizes and present a detailed characterization of the benefits.

Adoption of the 10 GbE Ethernet standard has been impeded by two important performance-oriented considerations: 1) processing requirements of common protocol stacks and 2) end-to-end latency. The overheads of typical software based protocol stacks on CPU utilization and throughput have been well evaluated in several studies. In this paper, we focus on end-to-end latency and present a detailed characterization across typical server system hardware and software stack components. We demonstrate that application level end-to-end latency with a 10 GbE connection can be as low as 10 microseconds for a single isolated request. The paper analyzes the components of the latency and discusses possible significant variations to the components under realistic conditions. We note that methods that are used to optimize throughput can often be responsible for the perception that Ethernet based latencies can be very high. Methods to pursue reducing the minimum latency and controlling the variations are presented.

Recent I/O technologies such as PCI-Express and 10 Gb Ethernet enable unprecedented levels of I/O bandwidths in mainstream platforms. However, in traditional architectures, memory latency alone can limit processors from matching 10 Gb inbound network I/O traffic. We propose a platform-wide method called direct cache access (DCA) to deliver inbound I/O data directly into processor caches. We demonstrate that DCA provides a significant reduction in memory latency and memory bandwidth for receive intensive network I/O applications. Analysis of benchmarks such as SPECWeb9, TPC-W and TPC-C shows that overall benefit depends on the relative volume of I/O to memory traffic as well as the spatial and temporal relationship between processor and I/O memory accesses. A system level perspective for the efficient implementation of DCA is presented.

Computation of optimum schedules for dynamic scheduling of tasks introduces an overhead delay in the processing time of the programs executed in an automated system. This is particularly so if serial scheduling algorithms are used. It is proposed that tasks be dynamically scheduled with the Lawler scheduling algorithm and that, to minimise the additional delay due to the computation of optimum schedules, a neural network be used for retrieving optimal solutions. A neural network architecture that can recognise binary vector representations of scheduling problems and retrieve optimal schedules in negligible time is described.>