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Tom Tsan-Kuo Tarng

dblp:79/6629 · DBLP profile ↗
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2ranked-venue papers
1as first author
0since 2021 · last 1984
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 100%
Theoretical computer science
2 papers
Mathematical optimization · 54% Graph algorithms and graph theory · 46%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
physical design		 0.021984
An Efficient Single-Row Routing Algorithm · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1984
Single-Layer Routing for VLSI: Analysis and Algorithms · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1983
Electronic design automation › physical design
routing		 0.021984
An Efficient Single-Row Routing Algorithm · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1984
Single-Layer Routing for VLSI: Analysis and Algorithms · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1983
Electronic design automation › physical design › routing › channel routing
single-row routing		 0.011984
An Efficient Single-Row Routing Algorithm · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1984
Electronic design automation › physical design › routing › VLSI routing
single-layer routing		 0.011983
Single-Layer Routing for VLSI: Analysis and Algorithms · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1983
Mathematical optimization
combinatorial optimization		 0.011984
An Efficient Single-Row Routing Algorithm · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1984
Graph algorithms and graph theory › planar graphs
planarity testing		 0.011983
Single-Layer Routing for VLSI: Analysis and Algorithms · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1983

Methods — techniques the papers use, named apart from their topics

interval graphical representation · 0.0heuristic algorithm · 0.0
YearPublicationVenuePosition
1984 An Efficient Single-Row Routing Algorithm
abstract
In this paper, we present a heuristic algorithm for single-row routing. Our approach is based on the interval graphical representation of the given net list. The objective function for minimization is the street congestion. The problem is known to be intractable in the sense of NP-completeness, thus a polynomial-time heuristic algorithm is proposed. It has been implemented and tested with various examples. So far it has always produced optimal solutions.
Tom Tsan-Kuo Tarng, Malgorzata Marek-Sadowska, Ernest S. Kuh
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
1983 Single-Layer Routing for VLSI: Analysis and Algorithms
abstract
In this paper we present a discussion of planarity testing and detailed single-layer routing. A program which implements the proposed algorithms for routing nets inside an arbitrarily shaped region has been written and tested. The results from this program are shown as examples.
Malgorzata Marek-Sadowska, Tom Tsan-Kuo Tarng
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2