In Computer Vision (CV), the deployment of Convolutional Neural Networks (CNNs) is often hindered by their substantial computational requirements and large labeled datasets. Self-supervised learning (SSL) serves as an effective approach to reducing the reliance on labeled data with the option of augmentation methods to infer and train CNNs. Excluding irrelevant features accelerates learning and improves optimization. We propose a Field-Programmable Gate Array (FPGA)-based hardware accelerator architecture tailored for SSL framework, leveraging its parallelism and reconfigurability to expedite block matching, optimize sparse convolutions, and manage data reuse, significantly improving resource and energy efficiency. The implementation and evaluation of our work on Xilinx ZCU102 FPGA working at 200 MHz confirm that the similarity finding part's FPGA accelerations with a low hardware overhead generates a latency of 0.0106 seconds, surpassing GPU and CPU, and in the sparse CNN's FPGA acceleration part, with the processing of VGG16 and ResNet50, compared with the related FPGA-based works, our design claims a maximum of 3.08× throughput improvement and 1.5× in energy efficiency.

This paper presents an ultra-low quiescent current power-wise buck converter for portable devices. To achieve high conversion efficiency across a wide range of load currents while minimizing the output ripple, the converter utilizes pulse-width modulation (PWM) and pulse-frequency modulation (PFM) control methods in heavy load and light load conditions, respectively. Time-division power supply technique is implemented to reduce the quiescent current. The converter incorporates an 8-bit built-in digital-to-analog converter (DAC), allowing selection of 256 different output voltages ranging from 0.5V to 1.8V in 5mV steps. Additionally, a transient enhancement circuit is included to expedite the transient response during mode switching. Fabricated in$0.18\boldsymbol {\mu }$m CMOS process, the proposed converter is capable of handling load currents from$1\boldsymbol {\mu }$A to 600mA with an input voltage of 2.5V to 5V. Featuring an ultra-low quiescent current of 55nA, the converter achieves a peak efficiency of 94.1% and maintains greater than 85% efficiency over a load range of$10\mu $A to 500mA when input and output are 3.6V and 1.8V, respectively.

Envelope tracking (ET) and average power tracking (APT) have been widely used as supply modulators of power amplifiers (PAs). To meet the new challenges brought by the 5G NR standard, the symbol power tracking (SPT) technique is proposed, which is more efficient than ET and more flexible than APT. For the application of subcarrier spacing (SCS) of 15-~60kHz in the frequency range 1 (FR1), this paper proposed a buck-boost SPT supply modulator with a transition time below 1.17-$\mu \text{s}$for 5G NR PA in the smartphone. The combination of three techniques improves the voltage transition speed. The charge-pump-based switching power modulator increases the output voltage higher than the battery voltage and offers a high voltage source for the auxiliary current paths (ACP). The ACP introduces additional currents to charge/discharge the 1-$\mu \text{F}$output capacitor. The end-point-prediction (EPP) scheme lets the compensator convert directly from one steady state to the next. This supply modulator circuit is designed and fabricated using 0.18-$\mu \text{m}$BCD technology. The output voltage range is 1–5-V. The maximum transition speed can be up to 0.37-$\mu \text{s}$/V and 0.15-$\mu \text{s}$/V for up-tracking and down-tracking, respectively.