Qiwei Zhao, Dong Li, Yanchi Liu, Wei Cheng, Yiyou Sun, Mika Oishi, Takao Osaki, Katsushi Matsuda, Huaxiu Yao, Chen Zhao, Haifeng Chen, Xujiang Zhao. Proceedings of the 63rd Annual Meeting of the Association for Computational Linguistics (Volume 1: Long Papers). 2025.

With the rapid proliferation of 5G technology and the exponential growth of IoT devices, federated learning is emerging as a typical paradigm in 5G IoT scenarios. However, traditional federated learning still faces numerous challenges in 5G IoT scenarios, including resource constraints on edge devices, strong data distribution heterogeneity, and stringent privacy protection requirements. To address these challenges, this paper proposes a lightweight federated learning privacy protection framework (FedDHKD) based on dynamic hierarchical knowledge distillation. The FedDHKD framework divides the model into a client-side feature extractor and a server-side classifier, and achieves efficient knowledge transfer and model compression through a dynamic knowledge distillation mechanism, thereby reducing communication overhead. Additionally, an optimization strategy based on model-agnostic meta-learning is introduced to enhance adaptability to heterogeneous data distributions and accelerate convergence. Furthermore, by adding Gaussian noise that satisfies differential privacy constraints to the low-dimensional features to be uploaded, lightweight and effective privacy protection is achieved. Finally, we evaluated the performance of the FedDHKD framework against baseline approaches across various datasets. Experimental results demonstrate that FedDHKD reduces communication overhead to approximately one-seventh of FedAvg while maintaining competitive model accuracy. This approach provides an effective solution for 5G IoT edge scenarios, achieving a balanced trade-off between performance, efficiency, and privacy.

High-resolution successive approximation register (SAR) analog-to-digital converters (ADCs) typically require bit weight calibration. The bit weight self-calibration technique is extensively used for its fully digital operation and low circuit complexity. Nonetheless, the comparator offset easily saturates the calibration circuit and leads to large bit weight errors in high-resolution scenarios, which needs to be cancelled in the analog domain. Moreover, the calibration needs to be repeated many times to reduce the circuit noise during calibration. These increase circuit complexity and calibration time. In this paper, a 16-bit SAR ADC with dual-segmental bit weight self-calibration is presented. The proposed calibration scheme increases the offset tolerance and suppresses the circuit noise during calibration. Therefore, precise analog-domain offset cancellation is not required, and the calibration time can be reduced. With these merits, the 16-bit SAR prototype designed in a 180-nm CMOS process achieves 16-bit linearity in only 370 clock cycles for calibration. The offset tolerance also increases to 7.5 mV. The extra analog circuit overhead for calibration reduces from high-resolution analog offset compensation circuits to only a comparator with a much-relaxed precision requirement, preserving the simple and scaling-friendly nature of SAR ADCs. With a sampling capacitance of 7 pF, the SAR ADC converts the signal at 4 MS/s with a peak signal-to-noise-and-distortion-ratio (SNDR) and a peak spurious-free dynamic range (SFDR) of 87.5 dB and 102 dBc, respectively. It consumes 10.1 mW from both 1.8-V and 3-V supplies and achieves a Schreier-figure-of-merit (FoM) of 170.5 dB at 4 MS/s.

This paper presents an efficient 8-MS/s 16-bit successive approximation register (SAR) analog-to-digital converter (ADC) with the proposed symmetric complementary switching (SCS) and split passive reference segmentation (SPRS). Conventionally, improving the SAR ADC speed compromises the signal-to-noise-and-distortion ratio (SNDR) and energy efficiency due to the high precision requirement and the sequential bit-cycling. In this design, the proposed SCS scheme reduces the parasitic capacitance in the sampling path and the settling error of the capacitive digital-to-analog converter (CDAC) with low SNDR and hardware penalties. In addition, to reduce reference ripples, active reference buffers generally consume high power while the passive methods may degrade the SNDR or occupy large areas. To efficiently reduce reference settling errors, an area-efficient SPRS is developed, which suppresses the reference settling error through the split reference segmentation. The prototype chip is fabricated in a 180-nm CMOS process and occupies an area of 0.57 mm2. Measurements show the ADC achieves a peak SNDR of 89.2 dB at 8 MS/s with a 9.5-mW power consumption. The Schreier-figure-of-merit (FoM) is 175.4 dB.

This article presents a new asynchronous least-significant-bit (LSB) averaging technique to improve the signal-to-noise ratio (SNR) of high-precision successive-approximation-register (SAR) analog-to-digital converters (ADCs) with high power efficiency. After normal conversion, a linear searching is performed to coarsely reduce the conversion error asynchronously. Subsequently, the comparator performs a complementary number of comparisons with unchanged residue voltages to further reduce the error. Compared to traditional statistical noise reduction methods, the proposed method is insensitive to process, voltage, and temperature (PVT) variations since it does not require knowledge of the noise distribution. Additionally, it only slightly reduces the signal bandwidth as only 10 extra cycles are required. Therefore, the proposed method is suitable for low-noise, high-resolution SAR ADCs with MS/s speed. The proposed technique is implemented on a 16-bit SAR ADC in a 180-nm CMOS process. Running at 1 MS/s with the proposed technique, the measured signal-to-noise-and-distortion ratio (SNDR) is improved from 91.8 dBFS to 95.1 dBFS, and the dynamic range (DR) is improved from 93.8 dB to 98.1 dB. With power increased by 6.2% and period increased by 11%, this technique leads to a 2.59 dB Schreier figure-of-merit (FoM$_{\mathrm {SNDR}}$) and a 3.59 dB FoMDR improvement. The ADC consumes 7.1 mW and achieves a 173.6-dB FoMSNDR and a 176.6-dB FoMDR, respectively.

We propose a variational Bayesian scheme for pruning convolutional neural networks in channel level. This idea is motivated by the fact that deterministic value based pruning methods are inherently improper and unstable. In a nutshell, variational technique is introduced to estimate distribution of a newly proposed parameter, called channel saliency, based on this, redundant channels can be removed from model via a simple criterion. The advantages are two-fold: 1) Our method conducts channel pruning without desire of re-training stage, thus improving the computation efficiency. 2) Our method is implemented as a stand-alone module, called variational pruning layer, which can be straightforwardly inserted into off-the-shelf deep learning packages, without any special network design. Extensive experimental results well demonstrate the effectiveness of our method: For CIFAR-10, we perform channel removal on different CNN models up to 74\% reduction, which results in significant size reduction and computation saving. For ImageNet, about 40% channels of ResNet-50 are removed without compromising accuracy.

This paper chiefly studies the problem of formation keep and Anti-Collision control of mobile multi-robots in an unknown environment. Algorithm combining global and local situation is used in path planning. Based on a global system path planning, each robot plans and performs its movement dynamically by adapting some distributive work mechanic according to the movement characteristics, thus when encounter some obstacles, the formation can be dissolved and then restore as soon as possible, and at the precondition of not to affect the team progress, destruction to the formation is reduced as much as possible, and thus multiple robot group can move safely and without collision.