EDBT 2026 Demo / reviewers in the wild / expert
Chiyoji Tanaka
dblp:80/10971
· DBLP profile ↗
4ranked-venue papers
2as first author
0since 2021 · last 1981
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
4 papers |
Electronic design automation · 100% |
Topics — the 6 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
physical design |
0.0 | 3 | 1981 | An integrated computer aided design system for gate array masterslices: Part 2 the layout design system MARS-M3 · DAC 1981 A hierarchical placement procedure with a simple blocking scheme · DAC 1979 An integrated computer aided design system for gate array masterslices: Part 1. Logic reorganization system LORES-2 · DAC 1981 |
Electronic design automation › logic synthesis
logic restructuring |
0.0 | 2 | 1981 | An integrated computer aided design system for gate array masterslices: Part 1. Logic reorganization system LORES-2 · DAC 1981 LORES - Logic Reorganization System · DAC 1978 |
Electronic design automation
logic synthesis |
0.0 | 2 | 1981 | An integrated computer aided design system for gate array masterslices: Part 1. Logic reorganization system LORES-2 · DAC 1981 LORES - Logic Reorganization System · DAC 1978 |
Electronic design automation › physical design
layout design |
0.0 | 1 | 1981 | An integrated computer aided design system for gate array masterslices: Part 2 the layout design system MARS-M3 · DAC 1981 |
Electronic design automation › physical design
placement |
0.0 | 1 | 1979 | A hierarchical placement procedure with a simple blocking scheme · DAC 1979 |
Electronic design automation › physical design
gate array design |
0.0 | 2 | 1981 | An integrated computer aided design system for gate array masterslices: Part 2 the layout design system MARS-M3 · DAC 1981 An integrated computer aided design system for gate array masterslices: Part 1. Logic reorganization system LORES-2 · DAC 1981 |
Methods — techniques the papers use, named apart from their topics
hierarchical placement · 0.0blocking scheme · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1981 | An integrated computer aided design system for gate array masterslices: Part 1. Logic reorganization system LORES-2
Chiyoji Tanaka, Shinichi Murai, Shunichiro Nakamura, Takuji Ogihara, Masayuki Terai, Kozo Kinoshita |
DAC | 1 |
| 1981 | An integrated computer aided design system for gate array masterslices: Part 2 the layout design system MARS-M3
Chiyoji Tanaka, Shinichi Murai, Hiroo Tsuji, Toshihiko Yahara, Kaoru Okazaki, Masayuki Terai, Reiji Katoh, Mikio Tachibana |
DAC | 1 |
| 1979 | A hierarchical placement procedure with a simple blocking scheme
Shinichi Murai, Hiroo Tsuji, Morio Kakinuma, Kazumichi Sakaguchi, Chiyoji Tanaka |
DAC | 5 |
| 1978 | LORES - Logic Reorganization System
Shunichiro Nakamura, Shinichi Murai, Chiyoji Tanaka, Masayuki Terai, Hideo Fujiwara, Kozo Kinoshita |
DAC | 3 |