EDBT 2026 Demo / reviewers in the wild / expert
Sankaralingam Panneerselvam
dblp:80/11029
· DBLP profile ↗
7ranked-venue papers
4as first author
1since 2021 · last 2023
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 5 · 4 first-authorSoftware engineering, systems software and programming languages · 3 · 1 first-author · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
5 papers |
Distributed systems · 52% Cloud and datacenter computing · 30% Storage systems · 12% | |
| Software engineering, system software, and programming languages
2 papers |
Software maintenance and evolution · 84% Operating systems · 16% |
Topics — the 8 heaviest of 10, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Distributed systems
fault tolerance |
1.1 | 3 | 2023 | Defcon: Preventing Overload with Graceful Feature Degradation · OSDI 2023 Maelstrom: Mitigating Datacenter-level Disasters by Draining Interdependent Traffic Safely and Efficiently · OSDI 2018 Bolt: Faster Reconfiguration in Operating Systems · USENIX ATC 2015 |
Distributed systems › fault tolerance › resilience
graceful degradation |
0.7 | 1 | 2023 | Defcon: Preventing Overload with Graceful Feature Degradation · OSDI 2023 |
Cloud and datacenter computing › datacenter operations
datacenter reliability |
0.3 | 1 | 2018 | Maelstrom: Mitigating Datacenter-level Disasters by Draining Interdependent Traffic Safely and Efficiently · OSDI 2018 |
Software maintenance and evolution › software evolution › software adaptation
software reconfiguration |
0.2 | 1 | 2015 | Bolt: Faster Reconfiguration in Operating Systems · USENIX ATC 2015 |
Storage systems
file systems |
0.2 | 1 | 2014 | Aerie: flexible file-system interfaces to storage-class memory · EuroSys 2014 |
Storage systems › file systems › file system design
persistent memory file system |
0.2 | 1 | 2014 | Aerie: flexible file-system interfaces to storage-class memory · EuroSys 2014 |
Processor architecture and microarchitecture › multicore design › heterogeneous multicore
asymmetric multicore |
0.1 | 1 | 2012 | Chameleon: operating system support for dynamic processors · ASPLOS 2012 |
Memory systems
non-volatile memory |
0.1 | 1 | 2014 | Aerie: flexible file-system interfaces to storage-class memory · EuroSys 2014 |
Methods — techniques the papers use, named apart from their topics
turbo boost · 0.3core fusion · 0.3kernel bypass · 0.2direct access · 0.2
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2023 | Defcon: Preventing Overload with Graceful Feature Degradation
Justin Meza, Thote Gowda, Ahmed Eid, Tomiwa Ijaware, Dmitry Chernyshev, Md Nazim Uddin, Rohan Das 0003, Chad Nachiappan, Sari Tran, Shuyang Shi, Tina Luo, David Ke Hong, Sankaralingam Panneerselvam, Hans Ragas, Svetlin Manavski, Francois Richard |
OSDI | 14 |
| 2018 | Maelstrom: Mitigating Datacenter-level Disasters by Draining Interdependent Traffic Safely and Efficiently
Kaushik Veeraraghavan, Justin Meza, Scott Michelson, Sankaralingam Panneerselvam, Alex Gyori, Sonia Margulis, Daniel Obenshain, Shruti Padmanabha, Ashish Shah, Yee Jiun Song, Tianyin Xu |
OSDI | 4 |
| 2016 | Rinnegan: Efficient Resource Use in Heterogeneous ArchitecturesabstractCurrent processors provide a variety of different processing units to improve performance and power efficiency. For example, ARM's big.LITTLE, AMD's APUs, and Oracle's M7 provide heterogeneous processors, on-die GPUs, and on-die accelerators. However, the performance experienced by programs using these processing units can vary widely due to contention from multiprogramming, thermal constraints and other issues. In these systems, the decision of where to execute a task must consider not only execution time of the task, but also current system conditions. Sankaralingam Panneerselvam, Michael M. Swift |
PACT | 1 |
| 2016 | POSTER: Firestorm: Operating Systems for Power-Constrained ArchitecturesabstractHardware Trends.Moore's law paved the way for doubling the transistors in the same chip area with every generation.However, with the end of Dennard's scaling, voltage and hence the power draw of transistors is no longer dropping proportionally to size.As a result, modern processors cannot use all parts of the processor simultaneously without exceeding the power limit.This manifests as an increasing proportion of dark silicon [4].In other words, the compute capacity of current and future processors is and will be overprovisioned with respect to the available power.Power limits are influenced by different factors such as the capacity of power distribution infrastructure, battery supply limits, and the thermal capacity of the system.Power limits in datacenters can arise from underprovisioning power distribution units relative to peak power draw.Energy limits are also dictated by the limited capacity of batteries.However, in many systems, the primary limit comes not from the ability to acquire power, but instead from the ability to dissipate power as heat once it has been used.Thermal limits are dictated by the physical properties of the processor materials and also comfort of the user.Thus, power is limited to prevent processor chips from overheating, which can lead to thermal breakdown.As a result, the maximum performance of a system is limited by its cooling capacity, which determines its ability to dissipate heat.Cooling capacity varies across the computing landscape, from servers with external chilled air to desktops with large fans to laptops to fan-less mobile devices.Current Support.Processors support mechanisms to enforce both power and temperature limits.For example, recent Intel processors provide Running Average Power Limit (RAPL) counters to enforce a power limit on the entire processor [1].In software, power capping services, such as the Linux power capping framework uses these limits to control power usage.Processor vendors define Thermal Design Power (TDP) metric for every processor model to guide the requirements of the cooling system needed to dissipate power.Most processors have a safeguard mechanism that throttles the processor by reducing the frequency or duty Sankaralingam Panneerselvam, Michael M. Swift |
PACT | 1 |
| 2015 | Bolt: Faster Reconfiguration in Operating Systems
Sankaralingam Panneerselvam, Michael M. Swift, Nam Sung Kim |
USENIX ATC | 1 |
| 2014 | Aerie: flexible file-system interfaces to storage-class memoryabstractStorage-class memory technologies such as phase-change memory and memristors present a radically different interface to storage than existing block devices. As a result, they provide a unique opportunity to re-examine storage architectures. We find that the existing kernel-based stack of components, well suited for disks, unnecessarily limits the design and implementation of file systems for this new technology. Haris Volos 0001, Sanketh Nalli, Sankaralingam Panneerselvam, Venkatanathan Varadarajan, Prashant Saxena, Michael M. Swift |
EuroSys | 3 |
| 2012 | Chameleon: operating system support for dynamic processorsabstractThe rise of multi-core processors has shifted performance efforts towards parallel programs. However, single-threaded code, whether from legacy programs or ones difficult to parallelize, remains important. Proposed asymmetric multicore processors statically dedicate hardware to improve sequential performance, but at the cost of reduced parallel performance. However, several proposed mechanisms provide the best-of-both-worlds by combining multiple cores into a single, more powerful processor for sequential code. For example, Core Fusion merges multiple cores to pool caches and functional units, and Intel's Turbo Boost raises the clock speed of a core if the other cores on a chip are powered down. Sankaralingam Panneerselvam, Michael M. Swift |
ASPLOS | 1 |