EDBT 2026 Demo / reviewers in the wild / expert
I. Vandeweerd
dblp:80/1125
· DBLP profile ↗
2ranked-venue papers
2as first author
0since 2021 · last 1989
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 100% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
logic synthesis |
0.0 | 2 | 1989 | REDUSA: module generation by automatic elimination of superfluous blocks in regular structures · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1989 REDUSA: Module Generation by Automatic Elimination of Superfluous Blocks in Regular Structures · DAC 1989 |
Electronic design automation › physical design
module generation |
0.0 | 2 | 1989 | REDUSA: module generation by automatic elimination of superfluous blocks in regular structures · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1989 REDUSA: Module Generation by Automatic Elimination of Superfluous Blocks in Regular Structures · DAC 1989 |
Electronic design automation
hardware verification and test |
0.0 | 1 | 1989 | REDUSA: Module Generation by Automatic Elimination of Superfluous Blocks in Regular Structures · DAC 1989 |
Methods — techniques the papers use, named apart from their topics
automatic block elimination · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1989 | REDUSA: Module Generation by Automatic Elimination of Superfluous Blocks in Regular StructuresabstractThis paper presents a new approach to module generation. It is based on the observation that a function, realized by a module instance (e.g. a 16-bit multiplier) when restricted to a sub-function, can be realized by a reduction of the instance to a sub-instance (e.g. a 8-bit multiplier). This reduction is performed automatically by REDUSA. It offers important advantages in both the construction and verification aspects of module generators. I. Vandeweerd, Kris Croes, Luc Rijnders, Paul Six, Hugo De Man |
DAC | 1 |
| 1989 | REDUSA: module generation by automatic elimination of superfluous blocks in regular structuresabstractThis paper presents a new approach to module generation. It is based on the observation that a function, realized by a module instance (e.g. a 16-bit multiplier) when restricted to a sub-function, can be realized by a reduction of the instance to a sub-instance (e.g. a 8-bit multiplier). This reduction is performed automatically by REDUSA. It offers important advantages in both the construction and verification aspects of module generators. I. Vandeweerd, Kris Croes, Luc Rijnders, Paul Six, Hugo De Man |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |