In this paper, we propose a system that verifies the authenticity of users based on the manner in which they operate a computer mouse. To begin with, we introduce a recurrence plot representation for encoding the information available in the mouse dynamics. Two image representation variants are suggested, namely the symmetric and asymmetric recurrence plots. Another noteworthy contribution is a modified vision transformer architecture for this task that incorporates key adjustments such as the removal of class token and positional embeddings. Rather, we facilitate a local pattern classification by considering the use of feature aggregation strategy for decision making. Additionally, we incorporate an efficient attention mechanism within the transformer encoder, that reduces both computational and memory complexity by simplifying the attention process. To further boost model performance, we integrate the Gradient Harmonizing Mechanism with binary cross-entropy loss, which dynamically adjusts the loss function based on gradient magnitudes. The proposed system is evaluated on three publicly available datasets, and the results obtained are at par to state-of-the-art methods. To the best of our knowledge, the present proposal is the first of its kind to introduce the utility of recurrence plots in a modified transformer framework.

With the continuous improvement of on-chip integrated voltage regulators (IVRs) and fast, adaptive frequency control, dynamic voltage-frequency scaling (DVFS) transition times have shrunk from the microsecond to the nanosecond regime, providing immense opportunity to improve energy efficiency. The key to unlocking the continued improvement in V/f circuit technology is the creation of new, smarter DVFS mechanisms that better adapt to rapid fluctuations in workload demand.

The imminent end of Moore's Law demands increasing complexi-ty to enable continuing improvement in the cost and performance of electronic systems. Complex RTL designs lead to long simulation overheads, making it infeasible to explore large design spac-es. In this work, we present a flow of simulation tools for rapid, high-level, pre-RTL exploration to enable design-space exploration for physically-constrained systems. This flow updates several prior tools and introduces new tools to support optimization across multiple metrics: gem5, a widely-used microarchitecture and memory hierarchy simulator, for performance; McPAT, a generalized, ISA-agnostic power and area modeling tool; HotSpot, a temperature simulator; VoltSpot, a voltage droop simulator; and OldSpot, a planned lifetime and reliability simula-tor. By simulating a workload in gem5 and feeding its results into McPAT and then HotSpot, VoltSpot, and OldSpot, it is possible to explore the effects of workloads on systems with physical con-straints such as power or thermal budgets and lifetime targets without requiring complex RTL design or long RTL simulation.

3D-IC technology brings both the opportunities to continue the historical trend of integration-level scaling and the challenges to deliver power reliably and efficiently. Voltage-stacking (V-S), a charge-recycled power delivery scheme that connects the different layers' supply/ground nets into a series stack, provides a scalable solution to the 3D-IC power delivery wall. While prior work has extensively discussed the implementations of V-S at circuit-level, a cross-layer study that examines its system-level implications is missing. In this paper, we start with a circuit implementation of a charge-recycled voltage regulator and build an architecture-level model to study the costs and benefits of utilizing V-S in 3D-IC. Our study shows that by significantly improving the EM-lifetime of C4 and TSV array (e.g., up to 5x) while only marginally increasing the average-case voltage noise (e.g., 0.75% Vdd IR drop), V-S provides a scalable solution for many-layer 3D-IC's power delivery challenge.

Aside from the benefits it brings, 3D-IC technology inevitably exacerbates the difficulty of power delivery with volumetrically increasing power consumption. Recent work managed to “recycle” current within the 3D stack by linking the different layers' supply/ground nets into a series connection. This charge-recycled (also known as voltage-stacked, or V-S) scheme provides a scalable solution for 3D-IC's power delivery because it supports an arbitrary number of layers with a constant off-chip current demand. Although prior work has studied the circuit implementation of a V-S power delivery network (PDN) and its current-reduction benefits, a whole-system evaluation of V-S PDNs' transient voltage noise and a noise comparison between the V-S PDN and the traditional PDN are missing. In this paper, we build a system-level model to examine voltage-stacked 3D-ICs' transient noise and explore the impact of different PDN design parameters and workload behaviors. Our results show that compared with the traditional PDN scheme, V-S provides stronger isolation for cross-layer noise interference, which in turn grants higher performance benefits for run-time noise mitigation techniques, such as dynamic margin adaptation. We observe that, compared with traditional PDNs, V-S PDNs provide up to 60% lower transient noise in the worst-case scenario. Furthermore, we show that V-S PDNs significantly reduce the packaging cost, because their noise is almost insensitive to the package impedance (e.g., a 300% impedance increase only raises worst-case noise by less than 0.3% Vdd).

This paper presents a novel multi-output on-chip switched-capacitor (SC) DC-DC converter simultaneously providing two output voltages (2VDD/3 and VDD/3, in addition to the available full VDD) that enables the use of three different power modes for optimizing power/performance trade-offs: super-threshold (full VDD), near-threshold (2VDD/3) and sub-threshold (VDD/3). Unlike previously proposed SC converters, the multiple conversion ratios of the novel converter are achieved without changing the topology of the circuit, thus fewer components being needed to support multiple voltages. Above 84% and 70% efficiencies are obtained in simulation over a range of load currents from 0.4 mA to 5 mA, and from 0.4 mA to 1 mA, with conversion ratios of 2/3 and 1/3, respectively. The paper also presents a novel optimization method to save area by using unequally sized flying capacitors. The target application is for systems with discrete power modes; also for systems that use dithering to emulate a continuous range of voltages such as the Panoptic Dynamic Voltage Scaling (PDVS).

We propose the use of voltage stacking for addressing some of the power delivery issues for many-core processors. To demonstrate the effectiveness of our method we first design a proxy for a many-core stacked processor in the form of a regular structure using multiple ring oscillators where we can control the voltage, frequency and switching activity for individual rings. For intermediate voltage rail regulation, we propose a push pull-based switched capacitor regulator designed specifically for balancing the stacked loads. Detailed Spice simulation results for the prototype model show a 4× reduction in supply current when using 4 layers of voltage stacking. We further validate our method by designing a voltage-stacked structure using two PIC cores.