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James L. Lewandowski

dblp:80/1203 · DBLP profile ↗
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5ranked-venue papers
2as first author
0since 2021 · last 1992
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 1 first-authorComputer networks · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 100%
Computer networks
1 paper
Routing and switching · 60% Vehicular, aerial and satellite networks · 40%

Topics — the 12 heaviest of 12, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test
fault modeling
0.011992
Optimal diagnostic methods for wiring interconnects · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992
Electronic design automation
hardware verification and test
0.011992
Optimal diagnostic methods for wiring interconnects · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992
Electronic design automation › hardware verification and test › fault diagnosis
interconnect diagnosis
0.011992
Optimal diagnostic methods for wiring interconnects · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992
Electronic design automation › hardware verification and test › fault modeling
stuck-at fault
0.011992
Optimal diagnostic methods for wiring interconnects · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992
Electronic design automation › hardware verification and test
test generation
0.011992
Optimal diagnostic methods for wiring interconnects · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992
Electronic design automation
physical design
0.011984
A branch and bound algorithm for optimal pla folding · DAC 1984
Electronic design automation › logic synthesis › logic optimization
PLA folding
0.011984
A branch and bound algorithm for optimal pla folding · DAC 1984
Routing and switching › switching networks
multistage interconnection network
0.011983
SS/TDMA Time Slot Assignment with Restricted Switching Modes · IEEE Trans. Commun. 1983
Vehicular, aerial and satellite networks
satellite communication
0.011983
SS/TDMA Time Slot Assignment with Restricted Switching Modes · IEEE Trans. Commun. 1983
Vehicular, aerial and satellite networks › satellite communication
SS/TDMA
0.011983
SS/TDMA Time Slot Assignment with Restricted Switching Modes · IEEE Trans. Commun. 1983
Routing and switching
switching
0.011983
SS/TDMA Time Slot Assignment with Restricted Switching Modes · IEEE Trans. Commun. 1983
Routing and switching
time slot assignment
0.011983
SS/TDMA Time Slot Assignment with Restricted Switching Modes · IEEE Trans. Commun. 1983

Methods — techniques the papers use, named apart from their topics

boundary scan · 0.0combinatorial optimization · 0.0branch-and-bound · 0.0
YearPublicationVenuePosition
1992 Optimal diagnostic methods for wiring interconnects
abstract
The problem of generating minimum test sets for diagnosing faults in wiring interconnects on printed circuit boards is addressed. It is assumed that all the nets can be accessed in parallel or through a boundary-scan chain on the board. The fault model includes multiple stuck-at-hand faults. Three methods for three different diagnosis mechanisms are presented. All the diagnostic methods can be further improved by taking advantage of the structural information of wiring interconnects.>
Wu-Tung Cheng, James L. Lewandowski, Eleanor Wu
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2
1990 Diagnosis for wiring interconnects
abstract
The authors address the problem of generating minimum test sets for diagnosing faults in wiring interconnects on printed circuit boards. It is assumed that all the nets can be accessed in parallel or through a boundary-scan chain on the board. The fault model includes multiple stuck-at and short faults. Three methods for three different diagnosis mechanisms are presented. It is also pointed out that the self-diagnosis problem is the same as the concurrent error detection problem for asymmetric errors. Thus, the diagnostic methods considered are similar to the coding methods used in concurrent error detection. All the diagnostic methods can be extended to structural tests by taking advantage of the geometry of a circuit board to produce an efficient test.>
Wu-Tung Cheng, James L. Lewandowski, Eleanor Wu
ITC2
1986 ESIM/AFS : A Concurrent Architectural Level Fault Simulator
Scott Davidson 0001, James L. Lewandowski
ITC2
1984 A branch and bound algorithm for optimal pla folding
James L. Lewandowski, C. L. Liu 0001
DAC1
1983 SS/TDMA Time Slot Assignment with Restricted Switching Modes
abstract
The time-slot assignment problem for a satellite-switched time-division multiple access system where only a restricted set of all possible switching modes is to be used is studied. An efficient algorithm for finding an optimal assignment is proposed. Also, methods for selecting restricted sets of switching modes are presented.
James L. Lewandowski, Jane W.-S. Liu, C. L. Liu 0001
IEEE Trans. Commun.1