Demo Data from EDBT 2026 / reviewers in the wild / expert
Kenneth E. Hoganson
dblp:80/1862
· DBLP profile ↗
3ranked-venue papers
3as first author
0since 2021 · last 2002
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 first-authorApplied, interdisciplinary, general and emerging computing · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Performance modeling and evaluation · 39% Parallel and multicore computing · 30% Processor architecture and microarchitecture · 30% |
Topics — the 3 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Processor architecture and microarchitecture › clustered architecture
cluster-based multiprocessor |
0.0 | 1 | 1999 | Workload Execution Strategies and Parallel Speedup on Clustered Computers · IEEE Trans. Computers 1999 |
Parallel and multicore computing
parallel computing |
0.0 | 1 | 1999 | Workload Execution Strategies and Parallel Speedup on Clustered Computers · IEEE Trans. Computers 1999 |
Performance modeling and evaluation › parallel system performance
speedup modeling |
0.0 | 1 | 1999 | Workload Execution Strategies and Parallel Speedup on Clustered Computers · IEEE Trans. Computers 1999 |
Methods — techniques the papers use, named apart from their topics
heuristics · 0.0analytical modeling · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2002 | High-performance computer architecture and algorithm simulatorabstractThis simulation tool allows the user to explore different computer architectures with hardware support at any or all of five levels of parallelism, from intrainstruction (pipeline) through distributed n -tier client/server systems. The tool supports the simulation of various user-configurable architectures and interconnection networks, running a user-configurable and variable workload. This allows the student and the instructor to observe how performance changes through the five levels of parallelism with changes in either the architecture or workload. The successful use of the simulation tool in a variety of undergraduate courses at the author's institution is presented, along with examples, and a set of experiments. The simulator is a Java applet, which can be used from a Web browser, allowing anyone with an Internet connection access to the tool, without concern about student licensing requirements. The simulator is hosted at the author's institution with funding provided by a recent grant. Its design as an applet also allows improvements and enhancements to the software to be implemented and instantly made available to all users of the product. Kenneth E. Hoganson |
ACM J. Educ. Resour. Comput. | 1 |
| 2000 | Mapping Parallel Application Communication Topology to Rhombic Overlapping-Cluster Multiprocessors
Kenneth E. Hoganson |
J. Supercomput. | 1 |
| 1999 | Workload Execution Strategies and Parallel Speedup on Clustered ComputersabstractA model of system performance for parallel processing on clustered multiprocessors is developed which unifies multiprogramming with speedup and scaled-speedup. The model is used to explore processor to process allocation alternatives for executing a workload consisting of multiple processes. Heuristics are developed that relate cluster size to parallel fraction of a program and to process scaling factors. The basic analytical model is made more sophisticated by incorporating considerations that affect the realizable speedup, including explicit process scaling, Degree of Parallelism (DOP) as a discrete function, and communication overhead. New developments incorporate nonuniform workload, interconnection network probability of acceptance of requests, nonuniform memory access, and multithreaded processes. Kenneth E. Hoganson |
IEEE Trans. Computers | 1 |