Coupling capacitance between adjacent wires in on-chip busses significantly increases the average transition energy dissipation. This paper develops a mathematical model for a memoryless encoding scheme and proposes a novel partitioning method for reducing the transition energy. Specifically, for an 8-bit bus in 65 nm CMOS technology, we present an 11-wire solution that reduces energy dissipation by 22%. The proposed scheme achieves similar energy efficiency without increasing the complexity of the encoding and decoding circuitry when the bus is extended to 16, 32 and 64 bits.

Coupling capacitance between adjacent wires in on-chip interconnect significantly increases the average transition energy dissipation, and the maximum delay. This paper proposed a novel encoding scheme to, further, reduce the coupling energy dissipation, and delay. Specifically for 65nm CMOS technology, we present an 8-bit to 10-bit equivalent solution that reduces the energy dissipation by 55%, and delay by 24%, without any additional area penalty, while requiring a less complex circuit overhead when compared with transition pattern coding (TPC) scheme.

Fluctuations in intrinsic linear Vt, free of impact of parasitics, are measured for large arrays of NMOS and PMOS devices on a testchip in a 150nm logic technology. Local intrinsic σVT, free of extrinsic process, length and width variations, is random, and worsens with reverse body bias. Although the traditional area-dependent component is dominant, a significant component of the fluctuations in small devices depends only on device width or length.

Contradictory trends in the industrial design environment have increased uncertainty while decreasing the tolerance to uncertainty. Worst case design techniques, still widely used in industry, do not provide the accuracy required to design under these conditions. On the other hand, statistical design techniques do provide a significant improvement in accuracy, by virtue of their "circuit adaptive" behavior, but at a substantial cost in computational effort. One practical solution to improving the accuracy of worst case design without sacrificing efficiency is considered here. It integrates an efficient statistical circuit simulator with worst case design tools into a hierarchical performance design process. It employs two stages of worst case analysis, calibrated with statistical circuit simulation, serving as filters to screen out circuits that easily meet their performance requirements. This focuses the use of statistical circuit simulation on those circuits for which the improved accuracy provides significant benefit. This methodology has been applied with outstanding results in design and manufacturing.>

A practical methodology for the statistical design of complex, logic integrated circuit products is described.It virtually eliminates the overhead associated with statistical modeling by combining a fully automatic, computationallyefficient statistical circuit simulator and worst case simulation tools into a hierarchical design flow.

A standard format for transmitting profiles of semiconductor structures between sites and between tools is described. The standard, called the profile interchange format (PIF), is a flexible and hierarchical format, capable of storing descriptions of semiconductor structures such as those produced and used by process and device simulators. It can store detailed descriptions of the geometry, attribute profiles, material properties, and transient behavior of a single structure or a collection of structures. Two equivalent forms of the PIF are proposed to resolve conflicting demands placed on the format by its two primary uses, which are transmitting profiles between sites and local use as a database for process and device simulation. The 'intersite' form of the PIF, which can be viewed as an extension of the electronic design interchange between sites, most importantly, portability. The 'intertool' form of the PIF is, in concept, equivalent in descriptive capabilities to the intersite form, but is intended to accommodate the needs of profile interchange between tools, most importantly, efficient storage and access of data. The PIF in both modes can be extended and modified to accommodate local needs.>

A new approach for making process and device simulation tools easier to use is presented. Described is an integrated CAD system for process design in which users select applications rather than tools. CAD simulation methodologies for each application are stored in an applications database and supported by automatic execution modules in the system. A database of "seed files" for initial process parameters are also provided. Both execution automation and the content in user interfaces are tailored to the chosen application to provide for an exceptionally simple and efficient interface, one that minimizes user learning requirements.