Demo Data from EDBT 2026 / reviewers in the wild / expert
Abhinav Das
dblp:80/2879
· DBLP profile ↗
3ranked-venue papers
2as first author
0since 2021 · last 2006
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 2 first-authorSoftware engineering, systems software and programming languages · 2 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Processor architecture and microarchitecture · 56% Memory systems · 44% |
Topics — the 6 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems
cache |
0.1 | 1 | 2005 | Dynamic Helper Threaded Prefetching on the Sun UltraSPARC CMP Processor · MICRO 2005 |
Memory systems › cache › prefetching
data prefetching |
0.1 | 1 | 2005 | Dynamic Helper Threaded Prefetching on the Sun UltraSPARC CMP Processor · MICRO 2005 |
Processor architecture and microarchitecture › multithreading
helper thread prefetching |
0.1 | 1 | 2005 | Dynamic Helper Threaded Prefetching on the Sun UltraSPARC CMP Processor · MICRO 2005 |
Processor architecture and microarchitecture
multithreading |
0.1 | 1 | 2005 | Dynamic Helper Threaded Prefetching on the Sun UltraSPARC CMP Processor · MICRO 2005 |
Processor architecture and microarchitecture
chip multiprocessor |
0.0 | 1 | 2005 | Dynamic Helper Threaded Prefetching on the Sun UltraSPARC CMP Processor · MICRO 2005 |
Processor architecture and microarchitecture
dynamic optimization |
0.0 | 1 | 2005 | Dynamic Helper Threaded Prefetching on the Sun UltraSPARC CMP Processor · MICRO 2005 |
Methods — techniques the papers use, named apart from their topics
software scouting · 0.1dynamic binary optimization · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2006 | Region Monitoring for Local Phase Detection in Dynamic Optimization SystemsabstractDynamic optimization relies on phase detection for two important functions (1) To detect change in code working set and (2) To detect change in performance characteristics that can affect optimization strategy. Current prototype runtime optimization systems (J. Lu et al) compare aggregate metrics like CPI over fixed time intervals to detect a change in working set and a change in performance. While simple and cost-effective, these metrics are sensitive to sampling rate and interval size. A phase detection scheme that computes performance metrics by aggregating the performance of individually optimized regions can be misled by some regions impacting aggregate metrics adversely. In this paper, we investigate the benefits and limitations of using aggregate metrics for phase detection, which we call global phase detection (GPD). We present a new model to detect change in working set and propose that the scope of phase detection be limited to within the candidate regions for optimization. By associating phase detection to individual regions we can isolate the effects of regions that are inherently unstable. This approach, which we call local phase detection (LPD), shows improved performance on several benchmarks even when global phase detection is not able to detect stable phases. Abhinav Das, Jiwei Lu, Wei-Chung Hsu |
CGO | 1 |
| 2005 | Performance of Runtime Optimization on BLASTabstractOptimization of a real world application BLAST is used to demonstrate the limitations of static and profile-guided optimizations and to highlight the potential of runtime optimization systems. We analyze the performance profile of this application to determine performance bottlenecks and evaluate the effect of aggressive compiler optimizations on BLAST. We find that applying common optimizations (e.g. O3) can degrade performance. Profile guided optimizations do not show much improvement across the board, as current implementations do not address critical performance bottlenecks in BLAST. In some cases, these optimizations lower performance significantly due to unexpected secondary effects of aggressive optimizations. We also apply runtime optimization to BLAST using the ADORE framework. ADORE is able to detect performance bottlenecks and deploy optimizations resulting in performance gains up to 58% on some queries using data cache prefetching. Abhinav Das, Jiwei Lu, Howard Chen 0002, Jinpyo Kim, Pen-Chung Yew, Wei-Chung Hsu, Dong-yuan Chen |
CGO | 1 |
| 2005 | Dynamic Helper Threaded Prefetching on the Sun UltraSPARC CMP ProcessorabstractData prefetching via helper threading has been extensively investigated on simultaneous multi-threading (SMT) or virtual multi-threading (VMT) architectures. Although reportedly large cache latency can be hidden by helper threads at runtime, most techniques rely on hardware support to reduce context switch overhead between the main thread and helper thread as well as rely on static profile feedback to construct the help thread code. This paper develops a new solution by exploiting helper threaded prefetching through dynamic optimization on the latest UltraSPARC chip-multiprocessing (CMP) processor. Our experiments show that by utilizing the otherwise idle processor core, a single user-level helper thread is sufficient to improve the runtime performance of the main thread without triggering multiple thread slices. Moreover, since the multiple cores are physically decoupled in the CMP, contention introduced by helper threading is minimal. This paper also discusses several key technical challenges of building a lightweight dynamic optimization/software scouting system on the UltraSPARC/Solaris platform. Jiwei Lu, Abhinav Das, Wei-Chung Hsu, Santosh G. Abraham |
MICRO | 2 |