Multicore systems with Non-Uniform Memory Access (NUMA) architecture are getting popular in computer systems. Processor cores take longer time to access memories on remote NUMA nodes than on local nodes. Because of operating system kernel's memory allocation and load balancing activities, a process may be migrated across nodes and its allocated memory may scatter on several nodes. Remote memory access and resource contention cause significant performance degradation in multicore NUMA systems. In this study, to reduce contention for inter-node interconnect links and decrease remote memory access in NUMA systems, we enhance the kernel's inter-node load balancing by migrating suitable processes or light-weight processes (i.e. threads) between NUMA nodes. We further propose various selection policies that select processes for migration according to their memory usages, so that the selected process uses the least amount of page frames in the system and/or shares the least amount of memory with other processes. These processes are expected to incur less remote memory access and have least influence caused by migration. The Linux kernel is modified to incorporate the proposed policies in the enhanced inter-node load balancing procedure. Experimental results demonstrate that the system performance is successfully improved by effectively reducing remote memory access and resource contention.

The recent research works of dual-port SRAM have focused on developing new write-assist techniques to suppress the potential inter-port write disturbance under low operating voltage and high process variation. However, the testing related issues induced by those newly proposed write-assist techniques have not been discussed yet in the previous literatures. In this paper, we first implemented a new write-assist dual-port SRAM proposed in [10] by using a 28nm LP process and then discussed the faulty behavior of injecting different resistive-open defects into both the SRAM cell and write-assist circuit. Next, we developed new test methods to detect the hard-to-detect resistive-open defects and proposed a corresponding March-like algorithm that covers a widely used March C- as well as the proposed test methods. Last, the required DfT for the proposed test methods was also discussed.

Gate oxide short (GOS) has become a common defect for advanced technologies as the gate oxide thickness of a MOSFET is greatly reduced. The behavior of a GOS-impacted MOSFET is, however, complicated and difficult to be accurately modeled at the circuit level. In this paper, we first build a golden model of a GOS-impacted MOSFET by using technology CAD, and identify the limitation and inaccuracy of the previous GOS models. Next, we propose a novel circuit-level GOS model which provides a higher accuracy of its dc characteristics than any of the previous models and being is able to represent a minimum-size GOS-impacted MOSFET. In addition, the proposed model can fit the transient characteristics of a GOS by considering the capacitance change of the GOS-impacted MOSFET, which has not been discussed in previous work. Last, we utilize our proposed GOS model to develop a novel GOS test method for SRAMs, which can effectively detect the GOS defects usually escaped from the conventional IDDQ test and March test.

When CMOS technologies enter nanometer scale, FinFET has become one of the most promising devices because of the superior electrical characteristics. Nonetheless, due to the scaling of dielectric thickness and the occurring of line-edge roughness, FinFETs may suffer the gate oxide short. Gate oxide short is a defect that has been widely discussed in planar bulk MOSFETs. But for FinFETs, the defect characteristics have not been studied yet. In this paper, we investigate the fault behaviors of the gate oxide short in FinFETs. The investigation includes both tied-gate and independent-gate FinFETs. Based on the TCAD mixed-mode simulations, we discover that the gate oxide short in the two types of FinFETs causes different fault behaviors from each other. Compared to planar bulk MOSFETs, the fault behaviors are even more complex. In addition to the discussion at device level, we also discuss the corresponding SRAM testing. For detecting gate oxide short in FinFET SRAMs, we propose two new test methods. By using TCAD transient simulations, we prove the two methods' test efficacy of detecting the gate oxide shorts uncovered by traditional test methods.

Due to the demand of lower power, a lot of research effort has been devoted into developing new SRAM cell designs that can operate with low supply voltage. The new SRAM cell designs have their own cell structures and design techniques, which may result in different faulty behaviors than the conventional 6T SRAM. Accordingly, specialized test methods are usually required for the uncovered faults of traditional tests. In this paper, we focus on testing open defects in a new low-VMINdata-aware dynamic-supply 8T SRAM design. The new SRAM utilizes a data-aware dynamic-supply circuitry cooperating with two write-word-lines to assist the write and an independent read path to enhance the read-SNM. Based on the specific cell structure, we propose a novel test method for the open defects. The test method creates an in-cell self-attacking environment and can detect all the defects undetected by traditional tests in both the SRAM cell and the data-aware dynamic-supply circuitry. Also, the method requires much less test time when being compared to the traditional floating bit-line attacking method.

Due to the increasing demand of an extra-low-power system, a great amount of research effort has been spent in the past to develop an effective and economic subthreshold SRAM design. However, the test methods regarding those newly developed subthreshold SRAM designs have not yet been fully discussed. In this paper, we first categorize the subthreshold SRAM designs into three types, study the faulty behavior of open defects and address decoders faults on each type of designs, and then identify the faults which may not be covered by a traditional SRAM test method. We will also discuss the impact of open defects and threshold-voltage mismatch on sense amplifiers under subthreshold operations. A discussion about the temperature at test is also provided.

Due to the increasing demands of lower-power devices, a lot of research effort has been devoted to develop new SRAM cell designs that can be effectively and economically operated at the subthreshold region. However, each new SRAM cell design has its own cell structure and design techniques, which may result in different faulty behaviors than the conventional 6T SRAMs and require specialized test methods to detect those uncovered fault models. In this paper, we focus on developing the test methods for testing a new 9T subthreshold SRAM design, which utilizes single bit-line read/write, two write word-lines for writing different values, and a separate read path. A mixed march algorithm with different background and address-traverse directions is proposed to detect various uncovered fault models and validated through real test chips. A new specialized technique of floating bit-line attacking is also presented to detect the stability faults, which cannot be effectively detected by applying the conventional test methods, for the new 9T SRAM design.

Detecting stability faults has been a crucial task and a hot research topic for the testing of conventional super-threshold 6T SRAM in the past. When lowering the supply voltage of SRAM to the subthreshold region, the impact of stability faults may significantly change, and hence the test methods developed in the past for detecting stability faults may no longer be effective. In this paper, we first categorize the subthreshold-SRAM designs into different types according to their bit-cell structures. Based on each type, we then analyze the difference of its stability faults compared to the conventional super-threshold 6T SRAM, and discuss how the stability-fault test methods should be modified accordingly. A series of experiments are conducted to validate the effectiveness of each stability-fault test method for different types of subthreshold-SRAM designs.

This paper presents a novel pixel design for active matrix organic light emitting diode (AM-OLED) displays using nanocrystalline silicon thin-film transistors (TFTs). The proposed pixel design can effectively reduce the variation of its stored display data caused by the leakage current of nanocrystalline silicon TFTs, which can in turn increase the contrast resolution of AM-OLED displays. With a proper setting of its capacitors, the proposed pixel design can achieve a 5.55× reduction on its display-data variation while requiring only a 1.15× write time when compared to the typical pixel design. The aperture ratio resulting from the layout of the proposed pixel design can also be maintained above 40%, which satisfies the specification of most AM-OLED displays. A series of simulations as well as measurement results are provided to validate the effectiveness of the proposed pixel design.

Defect repair has become a necessary process to enhance the overall yield for memories since manufacturing a natural good memory is difficult in current memory technologies. This paper presents an yield-estimation scheme, which utilizes an induction-based approach to calculate the probability that all defects in a memory can be successfully repaired by a two-dimensional redundancy design. Unlike previous works, which rely on a time-consuming simulation to estimate the expected yield, our yield-estimation scheme only requires scalable mathematical computation and can achieve a high accuracy with limited time and space complexity. Also, the proposed estimation scheme can consider the impact of single defects, column defects, and row defects simultaneously. With the help of the proposed yield-estimation scheme, we can effectively identify the most profitable redundancy configuration for large memory designs within few seconds while it may take several hours or even days by using conventional simulation approach.

Due to the increasing demand of an extra-low-power system, a great amount of research effort has been spent in the past to develop an effective and economic subthreshold-SRAM design. However, the test methods regarding those newly developed subthreshold-SRAM designs have not yet been fully discussed. In this paper, we first categorize the subthreshold-SRAM designs into three types, study the faulty behavior of different open defects for each type of designs, and then identify the faults which may or may not be covered by a traditional SRAM test method. For those hard-to-detect faults, we will further discuss the corresponding test method according to different each type of subthreshold-SRAM designs. At last, a discussion about the temperature at test will also be provided.

For modern display systems, thorough testing of the TFT array is a critical element in yield management. However, for system-on-panel displays which integrate drivers, timing units, and controllers on the same substrate (usually glass) as the TFT array, access to the array data and scan lines is complicated. To reduce the tester complexity, we propose a low area overhead and offset compensated charge sensing capable source driver design which facilitates built-in TFT array charge sensing. To reduce the number of test access ports, a serial voltage readout scheme is proposed. Simulation results using LTPS technology are shown to validate the proposed technique.