This paper presents the first reported joint gate sizing and buffer insertion method for minimizing the delay of power constrained combinational logic networks that can incorporate a mixture of unbuffered and buffered gates (or mixture of CMOS and BiCMOS gates). In the method, buffered gates in a network are decided on by an iterative process that uses a sequence of sizing optimizations where after each sizing optimization an update to the selection of buffered gates is made. In this way, high drive capability buffered (i.e., BiCMOS) gates with sufficiently low fan-out are identified and replaced with a lower power unbuffered (i.e., CMOS) version. As well, the optimality of the final design is assessed based on a lower-bound delay value that is calculated. Experimental results have confirmed the efficiency and utility of the proposed method. In 8-b adder or 8/spl times/8 b multiplier networks, just two iterations are sufficient to achieve a delay that is at worst within 0.6% of its final optimized value and at worst within 10% of the lower-bound value. In the design of BiCMOS networks, it is seen that a speed advantage (at equivalent power) can be systematically achieved by using a mix of CMOS and BiCMOS gates versus using all CMOS or all BiCMOS gates and that this advantage increases with the tightness of the power constraint and with load capacitance.

This paper presents a method for optimizing BiCMOS logic networks that exploits the fact that such networks may use a mixture of both CMOS and BiCMOS gates. The method assumes a given network architecture and finds both the logic family and size for each gate so that total delay (power) is minimized subject to a power (delay) constraint. The method views a BiCMOS gate as a type of buffered CMOS gate and selects the logic family for each gate based on a sequence of gate/buffer sizing optimizations each formulated as a polynomial program. Thus, a high drive BiCMOS gate with a low fan-out can be identified and replaced with a lower power CMOS gate. For a 0.8 /spl mu/m BiCMOS process, an optimized mixed CMOS/BiCMOS 8-bit adder (8 /spl times/ 8 bit multiplier) is found to be up to 21% (17%) faster than the optimized CMOS version dissipating the same power.