This article presents an efficient method for modeling and analysis of memristor crossbar array circuit-based neuromorphic computing hardware. A novel volatile memristor-based artificial neuron circuit is proposed, realizing real-time generation of spike sequences, where the amplitude, width, and reserve time of the spikes are all adjustable. Based on proposed neuron circuits and nonvolatile memristor-based artificial synapses, a spike timing-dependent plasticity (STDP) circuit implementation with a simple spike-mapping method is proposed and used for a memristor crossbar array-based spiking neural network (SNN) circuit. A circuit model of a crossbar array combined with a partial equivalent element circuit (PEEC) and volume filament (VFI) is used to calculate the circuit capacitance, inductance, and resistance. It is demonstrated by a transient simulation of a crossbar array circuit that the proposed SNN method can perform image classification tasks, and the recognition accuracy decreases with the frequency increase. From the perspective of affecting the spike sequences and STDP rules, damage caused by device stochasticity, parasitic effects, and skin effect on SNN recognition performance is further analyzed and evaluated.

Spiking Neural Networks (SNNs) have garnered considerable attention as a potential alternative to Artificial Neural Networks (ANNs). Recent studies have highlighted SNNs’ potential on large-scale datasets. For SNN training, two main approaches exist: direct training and ANN-to-SNN (ANN2SNN) conversion. To fully leverage existing ANN models in guiding SNN learning, either direct ANN-to-SNN conversion or ANN-SNN distillation training can be employed. In this paper, we propose an ANN-SNN distillation framework from the ANN-to-SNN perspective, designed with a block-wise replacement strategy for ANN-guided learning. By generating intermediate hybrid models that progressively align SNN feature spaces to those of ANN through rate-based features, our framework naturally incorporates rate-based backpropagation as a training method. Our approach achieves results comparable to or better than state-of-the-art SNN distillation methods, showing both training and learning efficiency.

Multivariate Time Series (MTS) forecasting plays a vital role in various real-world applications, such as traffic management and predictive maintenance. Existing approaches typically model MTS data in either Euclidean or Riemannian space, limiting their ability to capture the diverse geometric structures and complex Spatio-Temporal (ST) dependencies inherent in real-world data. To overcome this limitation, we propose the Hybird Symmetric Positive-Definite Manifold Graph Neural Network (HSMGNN), a novel graph neural network-based model that captures data geometry within a hybrid Euclidean–Riemannian framework. To the best of our knowledge, this is the first work to leverage hybrid geometric representations for MTS forecasting, enabling expressive and comprehensive modeling of geometric properties. Specifically, we introduce a Submanifold-Cross-Segment (SCS) embedding to project input MTS into both Euclidean and Riemannian spaces, thereby capturing ST variations across distinct geometric domains. To alleviate the high computational cost of Riemannian distance, we further design an Adaptive-Distance-Bank (ADB) layer with a trainable memory mechanism. Finally, a Fusion Graph Convolutional Network (FGCN) is devised to integrate features from the dual spaces via a learnable fusion operator for accurate prediction. Experiments on three benchmark datasets demonstrate that HSMGNN achieves up to 13.8% improvement over state-of-the-art baselines in forecasting accuracy.

Spiking Neural Networks (SNNs) are emerging as a brain-inspired alternative to traditional Artificial Neural Networks (ANNs), prized for their potential energy efficiency on neuromorphic hardware. Despite this, SNNs often suffer from accuracy degradation compared to ANNs and face deployment challenges due to fixed inference timesteps, which require retraining for adjustments, limiting operational flexibility. To address these issues, our work considers the spatio-temporal property inherent in SNNs, and proposes a novel distillation framework for deep SNNs that optimizes performance across full-range timesteps without specific retraining, enhancing both efficacy and deployment adaptability. We provide both theoretical analysis and empirical validations to illustrate that training guarantees the convergence of all implicit models across full-range timesteps. Experimental results on CIFAR-10, CIFAR-100, CIFAR10-DVS, and ImageNet demonstrate state-of-the-art performance among distillation-based SNNs training methods. Our code is available at https://github.com/Intelli-Chip-Lab/snn_temporal_decoupling_distillation.

This article presents a novel four-port probe calibration method for on-wafer S-parameter measurement of microwave circuits and, for the first time, realizes measurement verification up to 110 GHz. The method regards the 64 error terms in the four-port probe calibration as an error matrix, which can be solved by a homogeneous equation system using a generalized scatter matrix theory. The calibration algorithm can consider the crosstalk between the probes and improve the calibration accuracy at high frequencies. This method only requires six calibration standards to complete the four-port probe calibration. Only one coupled differential line with a symmetric structure is needed as the Thru, which replaces the traditional U-shape and asymmetric Thru and effectively reduces the number of calibration standards used in the four-port probe calibration. In addition, the method combined with an optimization method accurately and efficiently calculates the parasitic parameters of the calibration standards at high frequencies. The proposed method is validated by three different devices under test (DUTs) up to 110 GHz. Their S-parameters obtained by the proposed method, including all the pure-mode and mode-conversion terms, have high accuracy in magnitude and phase, proving the correctness and convenience of this method.

Recent insights have revealed that rate-coding is a primary form of information representation captured by surrogate-gradient-based Backpropagation Through Time (BPTT) in training deep Spiking Neural Networks (SNNs). Motivated by these findings, we propose rate-based backpropagation, a training strategy specifically designed to exploit rate-based representations to reduce the complexity of BPTT. Our method minimizes reliance on detailed temporal derivatives by focusing on averaged dynamics, streamlining the computational graph to reduce memory and computational demands of SNNs training. We substantiate the rationality of the gradient approximation between BPTT and the proposed method through both theoretical analysis and empirical observations. Comprehensive experiments on CIFAR-10, CIFAR-100, ImageNet, and CIFAR10-DVS validate that our method achieves comparable performance to BPTT counterparts, and surpasses state-of-the-art efficient training techniques. By leveraging the inherent benefits of rate-coding, this work sets the stage for more scalable and efficient SNNs training within resource-constrained environments.

This paper presents the efficient systematic methods for modeling and analysis of spike signal sequence in crossbar arrays for neuromorphic computing chips. A novel spike signal sequence is proposed, where the ideal spike sequence with only spike time information in the original spiking neural network (SNN) algorithm is mapped onto actual spike waveform by stitching neighboring sequential spikes together with certain overlaps. We thoroughly investigate and analyze the performance of the input encoding as well as the implementation of spike timing dependent plasticity (STDP)-based SNN on memristor crossbar arrays with the proposed spike signal sequence. A detailed circuit model of a crossbar array, consisting of resistance, capacitance and inductance derived by the partial equivalent element circuit (PEEC) method, is created to simulate the training process of SNN. The proposed spike signal sequence is demonstrated that is able to achieve accurate input encoding as well as high recognition accuracy when it is used to perform the classification task on MNIST handwritten digits. The spike signal sequence is further analyzed and assessed in terms of the main factors affecting its encoding accuracy and the parasitic effects of crossbar arrays on its robustness.

This paper provides a comprehensive study of signal integrity issues in RRAM-based neuromorphic chip crossbar arrays due to interconnect parasitic. First, the parasitic parameters of the crossbar array are calculated by the partial equivalent element circuit (PEEC) method with an efficient unit-cell approach. Numerical experiments show that for a$50\times 50$array scale, this method consumes only 1.5% of the calculation time of the commercial software based 3D model, which translates to a calculation speed up of 72 times. Moreover, the PEEC circuit simulation results match well with those of the 3D model. Then, we investigate the effects of parasitic parameters such as capacitance and inductance, as well as the feature size of the crossbar array on signal integrity. All of them will lead to corresponding changes in parasitic effects, which in turn result in the most common signal integrity issues such as crosstalk, time delay and mutual capacitive coupling induced sneak path problem. Different from other studies, the excitation used in this paper is the neural spike signal generated by the Izhikevich neuron model, which is both rich in dynamic characteristics and high in computational efficiency. Finally, based on the study we propose a simple but effective design scheme for reduction of signal distortion, which can provide valuable design guidance for neuromorphic systems to achieve high performance and high computational accuracy.

This article presents a novel circuit modeling method for online training and testing process of the neuromorphic chip crossbar array based on the resistive random access memory (RRAM). A modified RRAM compact model is developed to realize the fast and accurate update of multiple conductance levels. Two training mechanisms with and without write-verify scheme are modeled and investigated for classifying MNIST handwritten digits and both achieve a good recognition accuracy of more than 96%. The parasitic model of the unit cell of interconnects is constructed by the domain decomposition method (DDM) and the partial equivalent element circuit (PEEC) method, which is suitable to build up a crossbar array of any size. The impact of parasitic effects of interconnects on the recognition accuracy with and without write-verify scheme is analyzed and compared. The weights trained with write-verify scheme show better robustness to parasitic noises but training with write-verify scheme spends a longer time processing the same amount of data.

A model development methodology for complex shaped on-wafer interconnects is presented. The equivalent circuit of the entire interconnect is obtained by cascading basic subsegment models. The extracted parameters are formulated into empirical expressions. Thus, the proposed model can be easily incorporated with commercial electronic design automation (EDA) tools. The accuracy of the model is validated by the on-wafer measurements up to 20 GHz.

This paper investigates the properties of the on-wafer interconnects built in a 0.18-/spl mu/m CMOS technology for RF applications. A scalable equivalent circuit model is developed. The model parameters are extracted directly from the on-wafer measurements and formulated into empirical expressions. The expressions are in functions of the length and the width of the interconnects. The proposed model can be easily implemented into commercial RF circuit simulators. It provides a novel solution to include the frequency-variant characteristics into a circuit simulation. The silicon-verified accuracy is proved to be up to 25 GHz with an average error less than 2%. Additionally, equivalent circuit model for longer wires can be obtained by cascading smaller subsections together. The scalability of the propose model is demonstrated.