In this paper, we present an algorithm for selecting implementations for rectangular modules given a placement of the modules in multiple rows. A module is a rectangle with pins located on the top and the bottom edges. An implementation of a module is specified by its dimension and a placement of the pins along the top and bottom edges of the module. Our algorithm accepts as input a placement of the modules and a set of possible implementations of each module, and selects an implementation for each module to minimize the total height of the layout. The time complexity of our algorithm is O(NrK/sup r/+K/sup 2/P), where K is the maximum number of implementations for each module, r is the number of rows, N is the total number of modules, and P is the number of pins in the channel. Our algorithm can be applied to the CMOS transistor placement, and has been implemented in the custom cell synthesis system of MCC. We have tested the algorithm on cells selected from the MCNC benchmarks and industry. Reductions of up to 19% in layout area were obtained.

Existing over-the-cell channel routers assume that the orientations of the cells are fixed. In practice, it is quite common that each cell can be horizontally flipped. This pin rearrangement flexibility should be used by over-the-cell routers to further reduce channel routing area. Given a placement of cells in multiple rows with pin terminals at the top and bottom edges of the cells and each cell can be flipped. The objective is to select an orientation for each cell and a set of net segments to be routed over the cells such that the final routing area is minimized. In this paper, we assume the HCVD cell model, i.e., power/ground buses run through the middle of each cell row horizontally and one layer is available for over-the-cell routing. For this model, it suffices to focus on over-the-cell routing for each individual cell row. We present a branch-and-bound optimal algorithm to maximize the total weight of the net segments to be routed in both upper and Lower over-the-cell regions. With minor modifications, our algorithm is applicable to simultaneously consider pin assignment and over-the-cell routing. The proposed algorithm has been implemented and tested on a set of industrial examples. Reduction in total channel densities of up to 37% was obtained using a reasonable amount of CPU time.>

In this paper we consider two channel pin assignment problems which take circuit performance into account. The first one is the module implementation selection problem. We are given a net span bound for each critical net and each module has several possible placements of its pins. Our objective is to minimize channel density while satisfying net span constraints. We proved that this problem is NP-complete. For the case when each module has at most 2 pin placements, the problem can be transformed to the 2-SAT problem and hence is polynomial time solvable. We present a heuristic based on this algorithm to solve the general case. The second problem we consider is the module shifting problem. We are given a set of modules whose relative ordering is fixed on each side of the channel but their exact positions are not fixed. We present a polynomial time algorithm to test the feasibility of satisfying the net span constraints by shifting the modules. The algorithm is based on formulating the problem as a special integer linear programming problem which is solvable in polynomial time. We also extend our algorithms to handle multiple channels.>

Existing over-the-cell channel routers assume that the orientations of the cells are fixed. In practice, it is quite common that each cell can be horizontally flipped. This pin rearrangement flexibility should be used by over-the-cell routers to further reduce channel routing area. Given a placement of cells in multiple rows with pin terminals at the top and bottom edges and each cell can be flipped. The objective is to select an orientation for each cell and a set of net segments to be routed over the cells such that the final routing area is minimized. We present an optimal algorithm to maximize the total weights of the net segments to be routed in over-the-cell routing regions.>

The authors present an algorithm for selecting implementations for rectangular modules given a placement of the modules in multiple rows. A module is a rectangle with terminals located on the top and the bottom edges. An implementation of a module is specified by its dimension and a placement of the terminals along the top and bottom edges of the module. The algorithm accepts as input a placement of the modules and a set of possible implementations of each module, and selects an implementation for each module to minimize the total height of the layout. The time complexity of the algorithm is specified. The authors also present two extensions of the algorithm. The algorithm can be applied to CMOS transistor placement and has been implemented in the custom cell synthesis system of the MCC Physical Satellite. The algorithm was tested on cells selected from the MCNC benchmarks and industry, and reductions of up to 19% in layout area were obtained.>

A description is given of an O(NL+L log L) time algorithm, where N is the total number of transistor chains and L is the channel length, to determine the orientation of each transistor chain such that the channel density is minimized. It is shown that the problem of flipping chains and subchains to minimize channel density can also be solved optimally. Finally, it is observed that the algorithm can be used to optimally solve a generalized channel routing problem. The algorithm has been implemented in the custom cell synthesis system of the MCC Physical Satellite. For the cells selected from industry, the algorithm reduced channel density by 18%. They also tested the algorithm on several channel routing problems and reductions of up to 30% in channel density were obtained.>