Time-domain macromodeling represents an effective technique for generating compact models of the linear time-invariant portion of complex electromagnetic systems. Among the various techniques, a well-known one involves the computation of the port impulse response at the system’s ports, which is then used for calculating convolution integrals. Such computation is typically slow. Recently, a method has been proposed to accelerate such computation by exploiting a piecewise constant approximation of the impulse responses, leading to the so-called segment fast convolution approach. The contribution of the present work is twofold: i) to extend the aforementioned method to the case of piecewise linear approximation of the port impulse responses in the case of linear time-invariant circuits; ii) to define a highly efficient quasi-recursive convolution computation algorithm for both constant and linear piecewise approximations. Moreover, vectorization is exploited to further improve computational efficiency. The proposed convolution schemes are validated in the case of a simple two-port network and then applied to relevant case studies of large-scale electromagnetic systems. Specifically, Reconfigurable Intelligent Surfaces (RISs) and neuromorphic circuits are modeled and validated. The numerical evaluation shows that the proposed schemes are able to guarantee high accuracy together with significant computational speed-ups.

In this work, a stable and accurate model order reduction method for large-scale partial element equivalent circuit (PEEC) models with many delays is proposed. The method reduces the dimension of the original model by interpolating the original transfer function. The interpolation points are iteratively selected using a greedy algorithm. An efficient error estimator for the reduced transfer function makes the greedy algorithm very successful in both, properly selecting the interpolation points and tightly measuring the error of the reduced transfer function. The resulting reduced-order model is accurate both in the frequency and in the time domain. Numerical tests have shown that the reduced-order model successfully filters the instability behavior of the original model and exhibits stability over a large time interval.

A challenging and interesting issue for the solution of large electromagnetic problems is the efficient, sufficiently accurate modeling of the broadband skin-effect loss for conducting planes and 3-D shapes. The inclusion of such models in an electromagnetic (EM) solver can be very costly in compute time and memory requirements. These issues are particularly important for the class of signal, power, and noise integrity (NI) problems. In this paper, we concentrate on partial element equivalent circuit (PEEC)-type methods which are suitable for the solution of this class of problems. Progress has been made recently in the design of skin-effect models. The difficult issues are broadband frequency-domain or time-domain problems. These models are considered in this paper. We present several solution methods, and we compare results obtained with these approaches.

In this paper we prove that the generic half-T ladder network (LN), formed by a cascade of RC or RLC elementary cells, is a satisfactory model for transmission lines and interconnections. The determination of LN electrical characteristics (in particular the closed-form expressions of the step response) in terms of internal electrical parameters and number of cells has allowed to estimate, in an approximated but very accurate way, the time delay for RC and RLC terminated interconnections through new simple formulas. Numerical examples and comparisons with other metrics confirm the validity of the proposed method

High-speed electronic circuits are becoming more and more important in modern communication systems, thus leading to an increasing interest in printed circuit boards, interconnect, and packaging. Nowadays, full-wave numerical methods are widely used in order to investigate both signal integrity and electromagnetic compatibility issues arising in PCBs design. When broadband information is desired and transient effects dominate, it is more efficient using time domain numerical techniques, which may scale better than corresponding frequency-domain methods. This paper presents the derivation of the time domain partial element equivalent circuit (PEEC) method enhanced by the three-dimensional (3D) fast multipole method (FMM). It is shown that combining the full-wave time domain PEEC method with the FMM allows performing the analysis of electrically large electronic systems, which reduces both memory and CPU-time requirements. Several examples are presented confirming the capability of the proposed approach to provide a significant reduction of the computational complexity associated with the transient analysis of large systems.

A key use of the partial element equivalent circuit (PEEC) method is the solution of combined electromagnetic and circuit problems as they occur in many situations such as today's integrated circuit (VLSI) systems and as components in mobile devices. The method, which has been applied to a multitude of electrical interconnect and package problems, is very flexible since it is easy to add new features to the approach. However, faster solutions are of interest since the problems to be solved are continuously increasing size. A class of fast methods is evolving based on the faster evaluation of the matrix elements and the use of iterative or other matrix solvers of the resultant system for the frequency domain. Fast circuit matrix solvers are easier to obtain in the time domain than the frequency domain since the delay or retardation can be utilized to sparsify the circuit matrix. In this paper, we concentrate on techniques for the fast evaluation of the PEEC circuit element for both the frequency and time domain where possible since both are important for the solution of specific problems.

A method for de-embedding the scattering parameters matrix for single-end or differential through, buried, and blind via holes in multilayer printed circuit boards for high-speed digital applications is presented. The proposed technique starts from a measurement or simulation of the structure containing the discontinuity and, after the structure's partitioning, extracts the scattering parameters of the required discontinuity. The procedure is applied to different kinds of single-ended and differential via holes and is validated by measurements. The finite integration technique is used to perform the needed three-dimensional electromagnetic simulations. Due to its reduced CPU time, the proposed methodology is suitable for a parametric analysis on the electrical performance of the via hole discontinuities and it gives useful results for the extraction of accurate computer-aided design models.