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Suzana Stojkovic

dblp:80/4899 · DBLP profile ↗
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2ranked-venue papers
1as first author
1since 2021 · last 2023
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-author · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › logic synthesis
decision diagrams
0.112010
An Improved Algorithm for the Construction of Decision Diagrams by Rearranging and Partitioning the Input Cube Set · IEEE Trans. Computers 2010
Electronic design automation
logic synthesis
0.112010
An Improved Algorithm for the Construction of Decision Diagrams by Rearranging and Partitioning the Input Cube Set · IEEE Trans. Computers 2010
Electronic design automation › logic synthesis
programmable logic array
0.112010
An Improved Algorithm for the Construction of Decision Diagrams by Rearranging and Partitioning the Input Cube Set · IEEE Trans. Computers 2010

Methods — techniques the papers use, named apart from their topics

reordering · 0.1partitioning · 0.1
YearPublicationVenuePosition
2023 4-Valued spectral transforms implementation on GPU with Tensor Cores
Ivica Markovic, Suzana Stojkovic
J. Supercomput.2
2010 An Improved Algorithm for the Construction of Decision Diagrams by Rearranging and Partitioning the Input Cube Set
abstract
Decision diagrams (DDs) are a data structure that allows compact representation of discrete functions. The efficient construction of DDs in terms of space and time is often considered problem. A particular problem is that during the construction of a DD, a large number of temporary nodes are created. We address this problem in the case when the functions are specified in the PLA format. A common practice is to construct a DD by recursively processing all the cubes in PLA specification. The DD representing a subfunction defined by a single cube is merged with the DD for the subfunction defined by all the previously processed cubes. We proposed a method of reordering and partitioning the set of cubes in PLA specification that results in the reduction of both space and time complexities of the construction of DDs. First, we arrange cubes by their suffices. Then we partition the set of cubes, construct DDs for the subfunctions representing each partition separately, and merge them into a final DD. The reordering and partitioning ensures that these intermediary decision diagrams never exceed a certain size which is controlled by the size of the partitions. In this way, the number of operations on the nodes during the merging decision diagrams is reduced. This reduction results in a decrease both in the number of temporary nodes and construction time. The proposed method is used for the construction of DDs for the set of standard benchmark functions. The experiments show that the total number of created nodes is reduced on average by 34.65 percent, while the construction time is decreased by 48.6 percent.
Suzana Stojkovic, Dragan Jankovic, Radomir S. Stankovic
IEEE Trans. Computers1