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Peter D. Hortensius

dblp:80/5308 · DBLP profile ↗
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6ranked-venue papers
5as first author
0since 2021 · last 1990
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 6 · 5 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
4 papers
Electronic design automation · 56% Emerging computing paradigms · 38% Integrated circuit design · 3%

Topics — the 9 heaviest of 11, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test › design for testability
built-in self-test
0.031990
Cellular Automata-Based Signature analysis for Built-in Self-Test · IEEE Trans. Computers 1990
Cellular automata-based pseudorandom number generators for built-in self-test · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1989
Parallel Random Number Generation for VLSI Systems Using Cellular Automata · IEEE Trans. Computers 1989
Emerging computing paradigms
cellular automata
0.021989
Parallel Random Number Generation for VLSI Systems Using Cellular Automata · IEEE Trans. Computers 1989
Importance Sampling for Ising Computers Using One-Dimensional Cellular Automata · IEEE Trans. Computers 1989
Electronic design automation › hardware verification and test › test response compaction
signature analysis
0.011990
Cellular Automata-Based Signature analysis for Built-in Self-Test · IEEE Trans. Computers 1990
Electronic design automation
hardware verification and test
0.011989
Cellular automata-based pseudorandom number generators for built-in self-test · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1989
Emerging computing paradigms › unconventional computing
ising machine
0.011989
Importance Sampling for Ising Computers Using One-Dimensional Cellular Automata · IEEE Trans. Computers 1989
Electronic design automation › hardware verification and test › test generation › random test generation
pseudorandom test pattern generation
0.011989
Cellular automata-based pseudorandom number generators for built-in self-test · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1989
Emerging computing paradigms › approximate and stochastic computing › stochastic computing
random number generation
0.011989
Parallel Random Number Generation for VLSI Systems Using Cellular Automata · IEEE Trans. Computers 1989
Electronic design automation › hardware verification and test
test generation
0.011990
Cellular Automata-Based Signature analysis for Built-in Self-Test · IEEE Trans. Computers 1990
Integrated circuit design › digital circuit design
VLSI architecture
0.011989
Importance Sampling for Ising Computers Using One-Dimensional Cellular Automata · IEEE Trans. Computers 1989

Methods — techniques the papers use, named apart from their topics

cellular automaton · 0.0LFSR · 0.0pseudorandom sequence generation · 0.0monte carlo simulation · 0.0linear feedback shift register · 0.0importance sampling · 0.0cellular automata · 0.0
YearPublicationVenuePosition
1990 Percolation and Anomalous Transport as Tools in Analyzing Parallel Processing Interconnection Networks
Robert D. McLeod, J. J. Schellenberg, Peter D. Hortensius
J. Parallel Distributed Comput.3
1990 Cellular Automata-Based Signature analysis for Built-in Self-Test
abstract
Relevant signature analysis properties for elementary one-dimensional cellular automata are presented. It is found that cellular automata with cyclic-group rules provide signature analysis properties comparable to the LFSR (linear feedback shift register). A technique of using CALBO (cellular automata-based logic block observation) for both test pattern generation and signature analysis, in a similar manner to a typical BILBO (built-in block observation) implementation, is presented.>
Peter D. Hortensius, Robert D. McLeod, Howard C. Card
IEEE Trans. Computers1
1989 VLSI computing architectures for Ising model simulation
Peter D. Hortensius, Howard C. Card, Robert D. McLeod
Integr.1
1989 Importance Sampling for Ising Computers Using One-Dimensional Cellular Automata
abstract
The authors demonstrate that one-dimensional (1-D) cellular automata (CA) form the basis of efficient VLSI architectures for computations involved in the Monte Carlo simulation of the two-dimensional (2-D) Ising model. It is shown that the time-intensive task of importance sampling the Ising configurations is expedited by the inherent parallelism in this approach. The CA architecture further provides a spatially distributed set of pseudorandom numbers that are required in the local nondeterministic decisions at the various sites in the array. The novel approach taken to random-number generation can also be applied to a variety of other highly nondeterministic algorithms from many fields, such as computational geometry, pattern recognition, and artificial intelligence.>
Peter D. Hortensius, Howard C. Card, Robert D. McLeod, Werner Pries
IEEE Trans. Computers1
1989 Parallel Random Number Generation for VLSI Systems Using Cellular Automata
abstract
A novel random number generation (RNG) architecture of particular importance in VLSI for fine-grained parallel processing is proposed. It is demonstrated that efficient parallel pseudorandom sequence generation can be accomplished using certain elementary one-dimensional cellular automata (two binary states per site and only nearest-neighbor connections). The pseudorandom numbers appear in parallel from various cells in the cellular automaton on each clock cycle and pass standard empirical random number tests. Applications have been demonstrated in the design and analysis of special-purpose accelerators for Monte Carlo simulation of large intractable systems. In addition, significant advantages in pseudorandom built-in self-test of VLSI circuits using cellular automata based RNGs have been demonstrated.>
Peter D. Hortensius, Robert D. McLeod, Howard C. Card
IEEE Trans. Computers1
1989 Cellular automata-based pseudorandom number generators for built-in self-test
abstract
A variation on a built-in self-test technique is presented that is based on a distributed pseudorandom number generator derived from a one-dimensional cellular automata (CA) array. The cellular automata-logic-block-observation circuits presented are expected to improve upon conventional design for testability circuitry such as built-in logic-block operation as a direct consequence of reduced cross correlation between the bit streams that are used as inputs to the logic unit under test. Certain types of circuit faults are undetectable using the correlated bit streams produced by a conventional linear-feedback-shift-register (LFSR). It is also noted that CA implementations exhibit data compression properties similar to those of the LFSR and that they display locality and topological regularity, which are important attributes for a very large-scale integration implementation. It is noted that some CAs may be able to generate weighted pseudorandom test patterns. It is also possible that some of the analysis of pseudorandom testing may be more directly applicable to CA-based pseudorandom testing than to LFSR-based schemes.>
Peter D. Hortensius, Robert D. McLeod, Werner Pries, D. Michael Miller, Howard C. Card
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1