Demo Data from EDBT 2026 / reviewers in the wild / expert
Michael Slavkin
dblp:80/5391
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1999
—ORCID · unresolved
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › hardware verification and test
hardware verification |
0.0 | 1 | 1999 | A Methodology for the Verification of a "System on Chip" · DAC 1999 |
Electronic design automation › hardware verification and test › hardware verification
system-on-chip verification |
0.0 | 1 | 1999 | A Methodology for the Verification of a "System on Chip" · DAC 1999 |
Electronic design automation › hardware verification and test › hardware verification
verification methodology |
0.0 | 1 | 1999 | A Methodology for the Verification of a "System on Chip" · DAC 1999 |
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1999 | A Methodology for the Verification of a "System on Chip"abstractThis paper summarizes the verification effort of a complex ASIC designated to be an “all in one” ISDN network router. This ASIC is unique because it actually consists of many independent components, called “cores ” (including the processor). The integration of these components onto one chip results in an ISOC (Integrated System On a Chip). The complexity of verifying an ISOC is virtually impossible without a proper methodology. This paper presents the methodology developed for verifying the router. In particular, the verification method as well as the tools that were built to execute this method are presented. Finally, a summary of the verification results is given. Daniel Geist, Giora Biran, Tamarah Arons, Michael Slavkin, Yvgeny Nustov, Monica Farkas, Karen Holtz, Andy Long, Steve Barret |
DAC | 4 |