Demo Data from EDBT 2026 / reviewers in the wild / expert
Simon S. Liu
dblp:80/5610
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1996
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Integrated circuit design · 67% Electronic design automation · 33% |
Topics — the 6 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design › digital circuit design
arithmetic circuit design |
0.0 | 1 | 1996 | A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach · IEEE Trans. Computers 1996 |
Integrated circuit design
digital circuit design |
0.0 | 1 | 1996 | A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach · IEEE Trans. Computers 1996 |
Electronic design automation
logic synthesis |
0.0 | 1 | 1996 | A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach · IEEE Trans. Computers 1996 |
Integrated circuit design › digital circuit design › arithmetic circuit design
parallel multiplier |
0.0 | 1 | 1996 | A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach · IEEE Trans. Computers 1996 |
Integrated circuit design › digital arithmetic circuits › parallel multiplication
partial product reduction |
0.0 | 1 | 1996 | A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach · IEEE Trans. Computers 1996 |
Electronic design automation › high-level synthesis › hardware compilation
silicon compilation |
0.0 | 1 | 1996 | A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach · IEEE Trans. Computers 1996 |
Methods — techniques the papers use, named apart from their topics
algorithmic optimization · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1996 | A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic ApproachabstractThis paper presents a method and an algorithm for generation of a parallel multiplier, which is optimized for speed. This method is applicable to any multiplier size and adaptable to any technology for which speed parameters are known. Most importantly, it is easy to incorporate this method in silicon compilation or logic synthesis tools. The parallel multiplier produced by the proposed method outperforms other schemes used for comparison in our experiment. It uses the minimal number of cells in the partial product reduction tree. These findings are tested on design examples simulated in 1 /spl mu/ CMOS ASIC technology. Vojin G. Oklobdzija, David Villeger, Simon S. Liu |
IEEE Trans. Computers | 3 |